Page 1
NTMD3N08LR2
Power MOSFET
2.3 Amps, 80 Volts
N−Channel Enhancement−Mode
SO−8 Dual Package
Features
• Ultra Low On−Resistance Provides Higher Efficiency
♦ R
♦ R
• Low Reverse Recovery Losses
• Internal R
• Designed for Power Management Solutions in 42 V Automotive
System Applications
• I
DSS
• Avalanche Energy Specified
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Mounting Information for SO−8 Package Provided
• Pb−Free Package is Available
Applications
• Integrated Starter Alternator
• Electronic Power Steering
• Electronic Fuel Injection
• Catalytic Converter Heaters
MAXIMUM RATINGS (T
Drain−to−Source Voltage
Drain−to−Source Voltage (RGS = 1.0 mW)
Gate−to−Source Voltage − Continuous
Gate−to−Source Voltage −
Non−Repetitive (tp ≤ 10 ms)
Continuous Drain Current @ TA = 25°C
Pulsed Drain Current (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2) P
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 5.0 Vdc, Peak
IL = 7.0 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance −
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes for 10 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%
2. Mounted onto a 2″ square FR−4 board
(1in sq, oz. Cu 0.06″ thick single sided), t ≤ 5 seconds
= 0.215 W, VGS = 10 V
DS(on)
= 0.245 W, VGS = 5.0 V
DS(on)
= 50 W
G
and R
Specified at Elevated Temperature
DS(on)
Rating Symbol Value Unit
= 25°C unless otherwise noted)
J
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
D
stg
E
AS
R
q
JA
T
L
80
80
±15
±20
2.3
25
3.1 W
−55 to
+175
25 mJ
48 °C/W
260 °C
V
V
A
°C
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2.3 AMPERES
80 VOLTS
215 mW @ VGS = 5 V (Typ)
MARKING DIAGRAM &
PIN ASSIGNMENT
8
1
SOIC−8
CASE 751
STYLE 11
3N08 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
NTMD3N08LR2 SO−8 2500/Tape & Reel
NTMD3N08LR2G SO−8
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
D1 D1 D2 D2
8
3N08
AYWW G
G
1
S1 G1 S2 G2
†
2500/Tape & Reel
(Pb−Free)
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 7
1 Publication Order Number:
NTMD3N08LR2/D
Page 2
NTMD3N08LR2
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic Symbol Min Ty p Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Positive Temperature Coefficient
Zero Gate Voltage Drain Current
(VDS = 80 Vdc, VGS = 0 Vdc)
(VDS = 80 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate−Body Leakage Current
(VGS = 15 Vdc, VDS = 0 Vdc)
(VGS = −15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Negative Temperature Coefficient
Static Drain−to−Source On−State Resistance
(VGS = 5.0 Vdc, ID = 1.0 Adc)
(VGS = 10 Vdc, ID = 2.5 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc, TJ @ 150°C)
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C
Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C
SWITCHING CHARACTERISTICS (Notes 3 and 4)
Turn−On Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W)
Turn−On Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W)
Rise Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W)
Rise Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W)
Turn−Off Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W)
Turn−Off Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W)
Fall Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W)
Fall Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W)
Total Gate Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A)
Total Gate Charge (VDS = 40 Vdc, VGS = 10 Vdc, ID = 1.0 A)
Gate−Source Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Q
Gate−Drain Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Q
Threshold Gate Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Q
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage
(IS = 1.0 Adc, VGS = 0 V)
(IS = 1.0 Adc, VGS = 0 V, TJ = 150°C)
Reverse Recovery Time
(IS = 1.0 A, dIS/dt = 100 A/ms, VGS = 0 V)
Reverse Recovery Stored Charge
(IS = 1.0 A, dIS/dt = 100 A/ms, VGS = 0 V)
3. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
t
d(on)
t
d(off)
Q
G(TOT)
G(TH)
V
t
t
t
Q
iss
oss
rss
t
r
t
GS
GD
SD
rr
a
b
RR
80
−
−
99.8
−
−
Vdc
mV/°C
mAdc
−
−
−
−
2.0
250
nAdc
−
−
1.0
−
−
−
1.9
4.6
100
−100
3.0
−
Vdc
mV/°C
W
−
−
−
− 218 480
0.215
0.190
0.446
0.245
0.215
0.505
pF
− 54 150
− 15 50
−
−
−
−
−
−
f
−
−
−
−
21
13
62
95
52
47
48
104
5.1
8.8
34
−
104
−
85
−
81
−
9.0
15
ns
nC
− 0.95 −
− 2.75 −
− 0.35 −
Vdc
−
−
− 47 93
0.8
0.6
1.0
−
ns
− 25 −
− 22 −
− 0.067 0.134
mC
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NTMD3N08LR2
TYPICAL ELECTRICAL CHARACTERISTICS
5
4
3
2
, DRAIN CURRENT (AMPS)
1
D
I
0
8 V
7 V
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10 V
9 V
Figure 1. On−Region Characteristics
0.5
VGS = 5.0 V
0.4
0.3
0.2
0.1
, DRAIN−TO−SOURCE RESISTANCE (W)
0
DS(on)
R
0
1
ID, DRAIN CURRENT (AMPS)
4 V
5 V
6 V
VGS = 3.5 V
TJ = 25°C
1.6 1.8 21 1.2 1.40.6 0.80.40.20
TJ = 100°C
TJ = 25°C
TJ = −55°C
2345
, DRAIN CURRENT (AMPS)
D
I
0.3
0.25
0.2
0.15
0.1
0.05
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
6
VDS ≥ 10 V
5
4
3
2
1
0
0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 100°C
TJ = 25°C
TJ = − 55°C
563421
Figure 2. Transfer Characteristics
TJ = 25°C
VGS = 5.0 V
VGS = 10 V
0
02345
1
ID, DRAIN CURRENT (AMPS)
2.5
2
1.5
1
(NORMALIZED)
0.5
, DRAIN−TO−SOURCE RESISTANCE
0
DS(on)
R
Figure 3. On−Resistance versus
Drain Current and Temperature
VGS = 5.0 V
ID = 1.5 A
−25 0 25 50 75
TJ, JUNCTION TEMPERATURE (°C)
100−50
125 150 175
Figure 5. On−Resistance Variation with
Temperature
100,000
10,000
1000
100
, LEAKAGE (nA)
DSS
I
10
1
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3
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 175°C
TJ = 100°C
20 30 40 50 60
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
70
Figure 6. Drain−To−Source Leakage
Current versus Voltage
8010
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NTMD3N08LR2
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
the on−state when calculating t
and is read at a voltage corresponding to
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
600
500
400
300
200
C, CAPACITANCE (pF)
100
0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 VV
= 0 V
DS
C
iss
C
rss
C
rss
−505101520
V
Figure 7. Capacitance Variation
V
GS
DS
http://onsemi.com
4
TJ = 25°C
C
iss
C
oss
25−10
Page 5
NTMD3N08LR2
10
8
6
Q1
4
2
, GATE−TO−SOURCE VOLTAGE (V)
0
GS
V
0123 456789
Q2
QG, TOTAL GATE CHARGE (nC)
QT
ID = 1.0 A
TJ = 25°C
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
2.5
VGS = 0 V
TJ = 25°C
2
1000
VDD = 64 V
I
= 2.3 A
D
= 5.0 V
V
GS
100
t, TIME (ns)
10
1
1 10 100
t
r
td(off)
t
f
t
d(on)
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
1.5
1
0.5
, SOURCE CURRENT (AMPS)
S
I
0
0
0.2 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.4 0.6 0.8
Figure 10. Diode Forward Voltage versus Current
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NTMD3N08LR2
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V
) is exceeded, and that the
DSS
transition time (tr, tf) does not exceed 10 ms. In addition the
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
1
0.1
, DRAIN CURRENT (AMPS)
D
I
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
R
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
LIMIT
10 ms
100 ms
1 ms
10 ms
dc
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
− TC)/(R
).
JC
q
This power MOSFET can be safely used in switching
circuits with unclamped inductive loads. For reliable
operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
25
20
15
10
5
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
0
AS
1001010.1
E
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
100 125
ID = 2.3 A
150
175755025
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NTMD3N08LR2
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
THERMAL RESISTANCE
0.01
Rthja(t), EFFECTIVE TRANSIENT
0.1
0.05
0.02
0.01
Normalized to qja at 10s.
0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W
Chip
SINGLE PULSE
0.001
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
t
p
0.25 I
S
I
S
TIME
107.55 F1.7891 F0.3074 F0.0854 F0.0154 F
Ambient
1.0E+02 1.0E+03
Figure 14. Diode Reverse Recovery Waveform
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Page 8
−Y−
l
−Z−
NTMD3N08LR2
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
_
M
SOLDERING FOOTPRINT*
J
1.52
0.060
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
INCHES
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTMD3N08LR2/D
8
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