Datasheet ntljs4114n Datasheet

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Page 1

NTLJS4114N

Power MOSFET

30 V, 7.8 A, mCoolt Single N−Channel, 2x2 mm WDFN Package

Features

• WDFN Package Provides Exposed Drain Pad for Excellent Thermal

Conduction

• 2x2 mm Footprint Same as SC−88

• Lowest R

• 1.8 V R

Drive

DS(on)

• Low Profile (< 0.8 mm) for Easy Fit in Thin Environments

• This is a Pb−Free Device

Applications

• DC−DC Conversion

• Boost Circuits for LED Backlights

• Optimized for Battery and Load Management Applications in

Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc.

• Low Side Load Switch for Noisy Environment

MAXIMUM RATINGS (T

Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain

Current (Note 1)

Power Dissipation (Note 1)

Continuous Drain Current (Note 2)

Power Dissipation (Note 2)

Pulsed Drain Current Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) (Note 2) I Lead Temperature for Soldering Purposes

(1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).

2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu.

November, 2006 − Rev. 1

in 2x2 mm Package

DS(on)

Rating for Operation at Low Voltage Logic Level Gate

= 25°C unless otherwise noted)

Parameter

= 25°C

Steady

State

t ≤ 5 s T

Steady

State

t ≤ 5 s 3.3

Steady

State

= 85°C 4.4

= 25°C 7.8

= 25°C

= 85°C 2.6

= 25°C

= 10 ms

Symbol Value Unit

DSS

STG

30 V

±12 V

6.0

1.92

3.6

0.70 W

28 A

−55 to 150

3.0 A

260 °C

1 Publication Order Number:

°C

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MAX

(BR)DSS

30 V

Pin 1

JA = Specific Device Code M = Date Code G = Pb−Free Package

(Note: Microdot may be in either location)

DS(on)

35 mW @ 4.5 V 45 mW @ 2.5 V 55 mW @ 1.8 V

N−CHANNEL MOSFET

WDFN6

CASE 506AP

STYLE 1

ID MAX (Note 1)V

7.8 A

MARKING DIAGRAM

JAMG

2 3

PIN CONNECTIONS

(Top View)

ORDERING INFORMATION

Device Package Shipping

NTLJS4114NT1G WDFN6

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

3000/Tape & Ree

NTLJS4114N/D

†

6 5 4

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NTLJS4114N

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – t ≤ 5 s (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 4)

3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).

4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm

R R R

, 2 oz Cu).

65 38

180

°C/W

MOSFET ELECTRICAL CHARACTERISTICS (T

Parameter

Symbol Test Conditions Min Typ Max Unit

= 25°C unless otherwise noted)

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage

Temperature Coefficient Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

= 0 V, I

= 250 mA, Ref to 25°C

= 24 V, V

= 0 V, V

= 0 V

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage Negative Gate Threshold

Temperature Coefficient Drain−to−Source On−Resistance R

Forward Transconductance g

GS(TH)

GS(TH)/TJ

DS(on)

V V V

= VDS, I

= 4.5 V, I

= 2.5 V, I

= 1.8 V, I

= 16 V, I

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Threshold Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q Gate Resistance R

ISS OSS RSS

G(TOT)

G(TH)

= 0 V, f = 1.0 MHz,

= 4.5 V, V

= 2.0 A

= 15 V

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time Rise Time t Turn−Off Delay Time t Fall Time t

d(ON)

d(OFF)

= 4.5 V, V

= 2.0 A, R

DD G

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Recovery Voltage

Reverse Recovery Time t Charge Time t Discharge Time t Reverse Recovery Time Q

a b

VGS = 0 V, IS = 2.0 A

= 0 V, d

ISD/dt

= 1.0 A

5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

= 250 mA

30 V

20 mV/°C

TJ = 25°C 1.0 TJ = 85°C 10

= ±12 V ±100 nA

= 250 mA

0.4 0.55 1.0 V

3.18 mV/°C

= 2.0 A 20.3 35

= 2.0 A 25.8 45

= 1.8 A 35.2 55

= 2.0 A 8 S

650

115.5 70

8.5 13

= 15 V,

0.6

0.9

2.1

3.0

= 15 V,

= 3.0 W

TJ = 25°C 0.71 1.2 TJ = 85°C 0.58

14 35

= 100 A/ms,

8.0

6.0

5.0 nC

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NTLJS4114N

VGS = 1.6 V to 8 V

, DRAIN CURRENT (A)

1 0

0.5 51.5 2.5 3.5 4.5 5.5

0621

, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.03 VGS = 4.5 V

0.025

0.02

TYPICAL PERFORMANCE CURVES (T

1.5 V

TJ = 100°C

TJ = 25°C

1.4 V

1.3 V

1.2 V

, DRAIN CURRENT (A)

0.05

0.04

0.03

= 25°C unless otherwise noted)

VDS ≥ 10 V

TJ = 25°C

TJ = 100°C

, GATE−TO−SOURCE VOLTAGE (V)

TJ = 25°C

VGS = 1.8 V

VGS = 2.5 V

TJ = −55°C

1.5

20.5

2.5

0.015

TJ = −55°C

0.01

, DRAIN−TO−SOURCE RESISTANCE (W)

0.005

DS(on)

1.0

2.01.5

ID, DRAIN CURRENT (A)

Figure 3. On−Resistance versus Drain Current

1.6 ID = 2 A

= 4.5 V

1.4

1.2

1.0

(NORMALIZED)

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

−50 50250−25 75 125100

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

2.5

0.02

0.01

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

3.0 R

100000

10000

, LEAKAGE (nA)

DSS

1000

150

VGS = 4.5 V

ID, DRAIN CURRENT (A)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

TJ = 150°C

VGS = 0 V

TJ = 100°C

212104

6 8 14 16 18

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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NTLJS4114N

TYPICAL PERFORMANCE CURVES (T

1600

iss

1000

400

C, CAPACITANCE (pF)

rss

oss

−200 5 5 15 20 25

010

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

1000

VDD = 15 V I

= 3.0 A

= 4.5 V

100

VDS = 0 V

= 0 V

= 25°C

d(off)

= 25°C unless otherwise noted)

, GATE−TO−SOURCE VOLTAGE (VOLTS)

ID = 2 A T

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−T o−Source and Drain−To−Source

V oltage versus Total Charge

VGS = 0 V

TJ = 25°C

= 25°C

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

100

See Note 2 on Page 1

SINGLE PULSE T

= 25°C

= 150°C

0.1

, DRAIN CURRENT (AMPS)

0.01

0.1 1 100 V

, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward Biased

d(on)

, SOURCE CURRENT (AMPS)

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

Safe Operating Area

0.3 , SOURCE−TO−DRAIN VOLTAGE (V)

0.6

0.70.50.4

Figure 10. Diode Forward Voltage versus Current

10 ms 100 ms

1 ms 10 ms

0.8

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NTLJS4114N

1000

100

EFFECTIVE TRANSIENT THERMAL RESISTANCE

0.1

D = 0.5

0.2

0.1

0.05

0.02

0.01

TYPICAL PERFORMANCE CURVES (T

(pk)

SINGLE PULSE

t, TIME (s)

Figure 12. Thermal Response

DUTY CYCLE, D = t1/t

= 25°C unless otherwise noted)

See Note 2 on Page 1

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN

READ TIME AT t T

− TA = P

J(pk)

10.010.00001

(pk)

(t)

100 1000100.10.0010.00010.000001

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Page 6

PIN ONE

REFERENCE

0.10 C

0.08 C

BOTTOM VIEW

NTLJS4114N

PACKAGE DIMENSIONS

WDFN6 2x2

CASE 506AP−01

ISSUE B

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

SEATING

PLANE

A0.10 Cb1B

0.43

0.05 C

NOTE 5

A0.10 C

0.05 C

NOTE 3

1.25

0.34

0.65

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

5. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4.

6. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.

MILLIMETERS

DIMAMIN MAX

0.70 0.80

A1 0.00 0.05 A3 0.20 REF

b 0.25 0.35

0.51 0.61

2.00 BSC

1.00 1.20

2.00 BSC

1.10 1.30

0.65 BSC

0.15 REF

0.20 0.30

0.27 REF

0.65 REF

SOLDERING FOOTPRINT*

2.30

1.10

0.66

DIMENSIONS: MILLIMETERS

0.35

0.60

0.35

mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTLJS4114N/D