Datasheet nths4166n Datasheet

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NTHS4166N

Power MOSFET

30 V, 8.2 A, Single N-Channel, ChipFETt Package

Features

•Trench Technology

•Low R

•Leadless ChipFET Package has 40% Smaller Footprint than TSOP-6

•Excellent Thermal Capabilities

•This is a Pb-Free Device

Applications

•Load Switching

•DC-DC Converters

•Low Side Switching

to Minimize Conduction Losses

DS(on)

(BR)DSS

30 V

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Max

DS(on)

22 mW @ 10 V

27 mW @ 4.5 V

ID MaxV

8.2 A

MAXIMUM RATINGS (T

Parameter

Drain-to-Source Voltage V

Gate-to-Source Voltage V

Continuous Drain Current R

Power Dissipation R

Continuous Drain Current R

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current TA = 25°C,

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) R

Single Pulse Drain-to-Source Avalanche Energy T

= 20 Apk, L = 0.1 mH, RG = 25 W

Lead Temperature for Soldering Purposes

(1/8” from case for 10 s)

(Note 1)

(Note 2)

, t v 5 s

(Note 1)

= 25°C, VDD = 50 V, VGS = 10 V,

= 25°C unless otherwise noted)

Symbol Value Unit

DSS

= 25°C

= 85°C 4.8

= 25°C P

Steady

State

Steady

State

= 10 ms

= 25°C

= 85°C 3.6

= 25°C P

= 25°C

= 85°C 5.9

= 25°C P

STG

EAS 20 mJ

30 V

±20 V

6.6

1.5 W

4.9

0.8 W

8.2

2.2 W

32 A

-55 to 150

2.6 A

260 °C

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu.

2. Surface Mounted on FR4 Board using the minimum recommended pad size.

N-Channel MOSFET

MARKING DIAGRAM

AND PIN ASSIGNMENT

ChipFET

CASE 1206A

STYLE 1

466 = Specific Device Code M = Month Code G = Pb-Free Package

DDD

466 M

ORDERING INFORMATION

Device Package Shipping

NTHS4166NT1G ChipFET

3000/Tape & Reel

(Pb-Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

†

© Semiconductor Components Industries, LLC, 2007

December, 2007 - Rev. 0

1 Publication Order Number:

NTHS4166N/D

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NTHS4166N

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction-to-Ambient – Steady State (Note 3)

Junction-to-Ambient – t ≤ 5 s (Note 3)

Junction-to-Ambient – t ≤ 5 s (Note 4)

Junction-to-Foot (Drain) Steady State (Note 3)

3. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu.

4. Surface Mounted on FR4 Board using the minimum recommended pad size.

155

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Parameter Symbol Test Conditions Min Typ Max Units

OFF CHARACTERISTICS

Drain-to-Source Breakdown Voltage

Drain-to-Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate-to-Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

= 0 V, V

= 0 V, I

= 0 V, V

= 30 V

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain-to-Source On-Resistance R

Forward Transconductance g

GS(TH)

GS(TH)/TJ

DS(on)

= VDS, I

= 10 V, I

= 4.5 V, I

= 5 V, I

CHARGES AND CAPACITANCES

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate-to-Source Charge Q

Gate-to-Drain Charge Q

Total Gate Charge Q

Gate Resistance R

ISS

OSS

RSS

G(TOT)

G(TH)

G(TOT)

= 0 V, f = 1.0 MHz, V

= 4.5 V, V

= 10 V, V

= 15 V, I

SWITCHING CHARACTERISTICS (Note 6)

Turn-On Delay Time

Rise Time t

Turn-Off Delay Time t

Fall Time t

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

d(on)

d(off)

d(on)

d(off)

= 4.5 V, V

= 4.9 A, R

= 10 V, V

= 4.9 A, R

5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

= 250 mA

30 V

18.3 mV/°C

TJ = 25°C 1.0

TJ = 125°C 10

= ±20 V ±100 nA

= 250 mA

1.1 2.3 V

5.5 mV/°C

= 4.9 A 18 22

= 3.7 A 23 27

= 4.9 A 9.0 S

900

= 15 V

210

140

9.2

= 4.9 A

0.85

2.86

3.84

= 4.9 A 18 nC

1.6

= 3.0 W

= 15 V,

5.0

8.0

= 15 V,

= 3.0 W

4.0

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NTHS4166N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Parameter UnitsMaxTypMinTest ConditionsSymbol

DRAIN-SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

= 0 V, I

= 5.2 A

= 0 V, I

/dt = 100 A/ms

5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

TJ = 25°C 0.83 1.0 V

TJ = 125°C 0.7

= 5.2 A,

7.5

8.5

6.0 nC

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NTHS4166N

TYPICAL PERFORMANCE CURVES

10 V

, DRAIN CURRENT (AMPS)

0 0.5 1 1.5 2 3

4.5 V

3.6 V

3.4 V

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ = 25°C

2.5

3.2 V

3.0 V

2.8 V

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

0.095

0.085

0.075

0.065

0.055

0.045

0.035

0.025

, DRAIN-TO-SOURCE RESISTANCE (W)

0.015

0.005

DS(on)

246810

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID = 4.9 A T

= 25°C

Figure 3. On-Resistance vs. Gate-to-Source

Voltage

VDS ≥ 10 V

TJ = 125°C

, DRAIN CURRENT (AMPS)

12 3 4

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

0.030

TJ = 25°C

0.028

0.025

0.023

0.020

0.018

0.015

0.013

, DRAIN-TO-SOURCE RESISTANCE (W)

0.010

DS(on)

TJ = 25°C

TJ = -55°C

VGS = 4.5 V

VGS = 10 V

ID, DRAIN CURRENT (AMPS)

136 8 10 1257911

Figure 4. On-Resistance vs. Drain Current and

Gate Voltage

1.6

ID = 4.9 A V

= 10 V

1.4

1.2

1.0

(NORMALIZED)

0.8

, DRAIN-TO-SOURCE RESISTANCE

0.6

-50 0 50 100 150

DS(on)

-25 25 75 125

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On-Resistance Variation with

Temperature

10000

1000

, LEAKAGE (nA)

100

DSS

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VGS = 0 V

TJ = 150°C

TJ = 125°C

5101520 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. Drain-to-Source Leakage Current

vs. Drain Voltage

Page 5

1400

1200

1000

iss

800

600

400

C, CAPACITANCE (pF)

oss

200

rss

01015

DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

NTHS4166N

TYPICAL PERFORMANCE CURVES

VGS = 0 V

TJ = 25°C

25 30

, GATE-TO-SOURCE VOLTAGE (VOLTS)

0812416

Figure 8. Gate-To-Source and Drain-To-Source

ID = 4.9 A T

= 25°C

610 18214

QG, TOTAL GATE CHARGE (nC)

Voltage vs. Total Charge

1000

VDD = 15 V I

= 4.9 A

= 10 V

100

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

1 ms

VGS = 20 V SINGLE PULSE

, DRAIN CURRENT (AMPS)

0.01

0.1 10 100

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

1 25 125

TC = 25°C

0.1

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

d(off)

d(on)

10 ms

VGS = 0 V

TJ = 25°C

, SOURCE CURRENT (AMPS)

0.4 0.8

0.5 0.6 1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAIN-TO-SOURCE

, JUNCTION TEMPERATURE (°C)

75 100 15050

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.7 0.9

ID = 20 A

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Page 6

NTHS4166N

PACKAGE DIMENSIONS

ChipFETt

CASE 1206A-03

ISSUE H

8765

1234

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

0.05 (0.002)

4. GATE

5. SOURCE

6. DRAIN

7. DRAIN

8. DRAIN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL

8765

1234

AND VERTICAL SHALL NOT EXCEED 0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE.

DIMAMIN NOM MAX MIN

b 0.25 0.30 0.35 0.010 c 0.10 0.15 0.20 0.004 D 2.95 3.05 3.10 0.116 E 1.55 1.65 1.70 0.061 e 0.65 BSC

e1 0.55 BSC

L 0.28 0.35 0.42 0.011

MILLIMETERS

1.00 1.05 1.10 0.039

1.80 1.90 2.00 0.071 0.075 0.079

5° NOM

INCHES

NOM MAX

0.041 0.043

0.012 0.014

0.006 0.008

0.120 0.122

0.065 0.067

0.025 BSC

0.022 BSC

0.014 0.017

5° NOM

2.032

SOLDERING FOOTPRINTS*

0.08

2.032

0.08

1.727

0.068

2.362

0.093

0.635

0.025

2.362

0.093

PITCH

0.457

0.018

Basic

0.66

0.026

inches

0.457

0.018

Style 1

0.66

0.026

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ChipFET is a trademark of Vishay Siliconix

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTHS4166N/D