Datasheet nthd4p02f Datasheet

Download

Page 1

NTHD4P02F

l l

Brochure, BRD8011/D.

Power MOSFET and Schottky Diode

−20 V, −3.0 A, Single P−Channel with

3.0 A Schottky Barrier Diode, ChipFETt

Features

• Leadless SMD Package Featuring a MOSFET and Schottky Diode

• 40% Smaller than TSOP−6 Package with Similar Thermal

Characteristics

• Independent Pinout to each Device to Ease Circuit Design

• Ultra Low VF Schottky

• Pb−Free Package is Available

Applications

• Li−Ion Battery Charging

• High Side DC−DC Conversion Circuits

• High Side Drive for Small Brushless DC Motors

• Power Management in Portable, Battery Powered Products

MOSFET MAXIMUM RATINGS (T

Parameter Symbol Value Units

Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain

Current

Pulsed Drain Current

Power Dissipation

Continuous Source Current (Body Diode) I Operating Junction and Storage

Temperature Lead Temperature for Soldering Purposes

(1/8″ from case for 10 s)

Steady

State

t v 5 s T

= 10 ms

Steady

State

t v 5 s T

SCHOTTKY DIODE MAXIMUM RATINGS

(TJ = 25°C unless otherwise noted)

Parameter Symbol Value Units

Peak Repetitive Reverse Voltage V DC Blocking Voltage V Average Rectified

Forward Current

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

November, 2005 − Rev. 7

Steady

State

t v 5 s 3.0 A

= 25°C unless otherwise noted)

DSS

TJ, T

RRM

STG

= 25°C

= 85°C −1.6

= 25°C I

= 25°C

= 85°C 0.6

= 25°C 2.1

= 25°C

−20 V ±12 V

−2.2

−3.0 A

−9.0 A

1.1

−2.1 A

−55 to 150 °C

260 °C

20 V 20 V

2.2 A

1 Publication Order Number:

http://onsemi.com

MOSFET

(BR)DSS

−20 V

TYP

DS(on)

−130 mW @ −4.5 V 200 mW @ −2.5 V

ID MAXV

−3.0 A

SCHOTTKY DIODE

VR MAX IF MAXVF TYP

20 V

P−Channel MOSFET

PIN CONNECTIONS

A S

C3 = Specific Device Code M = Month Code G = Pb−Free Package

0.510 V

SCHOTTKY DIODE

ChipFET

CASE 1206A

STYLE 3

3.0 A

MARKING DIAGRAM

C D D

3 4

C3 M

8 7 6 5

ORDERING INFORMATION

Device Package Shipping

NTHD4P02FT1 ChipFET 3000/Tape & Ree NTHD4P02FT1G ChipFET

(Pb−free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification

3000/Tape & Ree

NTHD4P02F/D

†

Page 2

NTHD4P02F

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Units

Junction−to−Ambient (Note 1)

Steady State

t v 5 s 60

= 25°C

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).

110

°C/W

MOSFET ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Parameter Symbol Test Conditions Min Typ Max Units

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

= 0 V, I

= −16 V, V = −16 V, V

= 0 V, V

= −250 mA

= 0 V, TJ = 25°C

= 0 V, TJ = 85°C

= ±12 V ±100 nA

−20 −23 V

−1.0

−5.0

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage V Drain−to−Source On− Resistance R

Forward Transconductance g

GS(TH)

DS(on)

= VDS, I

= −4.5, I = −2.5, I

= −10 V, I

= −250 mA

= −2.2 A 0.130 0.155

= −1.7 A 0.200 0.240

= −1.7 A 5.0 S

−0.6 −0.75 −1.2 V

CHARGES AND CAPACITANCES

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Threshold Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q

ISS OSS RSS

G(TOT)

G(TH)

GS GD

= 0 V, f = 1.0 MHz,

= −4.5 V, V

= −10 V

= −2.2 A

= −10 V,

185 300

95 150 30 50

3.0 6.0

0.2

0.5

0.9

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time t

d(ON)

Rise Time t Turn−Off Delay Time t

d(OFF)

Fall Time t

= −4.5 V, V = −2.2 A, R

= −16 V,

= 2.5 W

7.0 12 13 25 33 50 27 40

DRAIN−SOURCE DIODE CHARACTERISTICS (Note 2)

Forward Diode Voltage V

Reverse Recovery Time tRR Charge Time ta 10

Discharge Time tb 22

= 0 V,

= −2.1 A

dIS/dt = 100 A/ms

= 0 V, I

= −2.1 A ,

−0.85 −1.15 V

Reverse Recovery Charge QRR 15 nC

SCHOTTKY DIODE ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Parameter Symbol Test Conditions Min Typ Max Units

Maximum Instantaneous Forward Voltage V

Maximum Instantaneous Reverse Current I

= 0.1 A 0.425

= 0.5 A 0.480

= 1.0 A 0.510 0.575

= 10 V 1.0

= 20 V 5.0

Maximum Voltage Rate of Change dv/dt VR = 20 V 10,000 V/ns Non−Repetitive Peak Surge Current I

FSM

Halfwave, Single Pulse, 60 Hz 23 A

2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

3. Switching characteristics are independent of operating junction temperatures.

http://onsemi.com

Page 3

NTHD4P02F

DRAIN−TO−SOURCE RESISTANCE (

)

TYPICAL MOSFET PERFORMANCE CURVES (T

VGS = −6 V to −3 V VGS = −2.4 V

TJ = 25°C

−2 V

= 25°C unless otherwise noted)

VDS ≥ −10 V

−2.2 V

−1.8 V

−1.6 V

DRAIN CURRENT (AMPS)

−I 0

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.5

0.4

DRAIN CURRENT (AMPS)

−1.4 V

−1.2 V

−I 0

632

0.5

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.25

ID = −2.1 A TJ = 25°C

0.225

TJ = 25°C

TC = −55°C

25°C

100°C

21.5 2.5

Figure 2. Transfer Characteristics

VGS = −2.5 V

0.2

0.3

0.2

0.175

0.15 VGS = −4.5 V

0.1

DS(on),

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.125

DRAIN−TO−SOURCE RESISTANCE (W)

0.1

0.5 1.5 2.5 3.5

DS(on),

−ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.6 ID = −2.1 A VGS = −4.5 V

1.4

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

10000

VGS = 0 V

TJ = 150°C

1000

1.2

DRAIN−TO−SOURCE

0.8

DS(on),

RESISTANCE (NORMALIZED)

0.6

−50 0−25 25

Figure 5. On−Resistance Variation with

50 125100

75 150

−TJ, JUNCTION TEMPERATURE (°C)

Temperature

, LEAKAGE (A)

100

DSS

−I

24 8

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

TJ = 100°C

610 1814

vs. Voltage

http://onsemi.com

Page 4

NTHD4P02F

TYPICAL MOSFET PERFORMANCE CURVES (T

600

500

VDS = 0 V VGS = 0 V

ISS

TJ = 25°C

400

RSS

300

200

C, CAPACITANCE (pF)

100

OSS

−VGS−V

510 10

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

1000

VDD = −16 V ID = −2.1 A VGS = −4.5 V

100

d(OFF)

t, TIME (ns)

d(ON)

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

= 25°C unless otherwise noted)

−V

GATE−TO−SOURCE VOLTAGE (V)

GS,

−V

01234

Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

2.5 VGS = 0 V TJ = 25°C

1.5

0.5

, SOURCE CURRENT (AMPS)

−I 0

−VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

QG, TOTAL GATE CHARGE (nC)

0.70.50.3

−V

ID = −2.1 A TJ = 25°C

0.9

DRAIN−TO−SOURCE VOLTAGE (V)

DS,

−V

1.0

D = 0.5

0.2

0.1

0.05

0.02

0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W

Chip

Normalized to qja at 10s.

0.01

r(t), NORMALIZED EFFECTIVE

SINGLE PULSE

TRANSIENT THERMAL RESISTANCE

107.55 F1.7891 F0.3074 F0.0854 F0.0154 F

Ambient

0.01

1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 1.0E+02 1.0E+03

t, TIME (s)

Figure 11. Thermal Response

http://onsemi.com

Page 5

NTHD4P02F

, INSTANTANEOUS FORWARD

REVERSE CURRENT (AMPS)

TYPICAL SCHOTTKY PERFORMANCE CURVES (T

TJ = 150°C

CURRENT (AMPS)

0.1

0.20

0.40

VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 12. Typical Forward Voltage Figure 13. Maximum Forward Voltage

1E−3

100E−6

10E−6

1E−6

TJ = 150°C

TJ = 100°C

TJ = 25°C

TJ = −55°C

0.60 0.80

TJ = 150°C

CURRENT (AMPS)

, INSTANTANEOUS FORWARD

0.1

0.20 VF, MAXIMUM INSTANTANEOUS FORWARD

1.0E+1

1.0E+0

1.0E−1

1.0E−2

1.0E−3

1.0E−4

= 25°C unless otherwise noted)

TJ = 25°C

0.40 0.60 0.80

VOLTAGE (VOLTS)

TJ = 150°C

TJ = 100°C

100E−9

10E−9

AVERAGE FORWARD CURRENT (AMPS)

3.5

2.5

1.5

0.5

TJ = 25°C

VR, REVERSE VOLTAGE (VOLTS)

Figure 14. Typical Reverse Current

45 145

square wave

Ipk/Io = p Ipk/Io = 5

Ipk/Io = 10 Ipk/Io = 20

65 125105

85 165

TL, LEAD TEMPERATURE (°C)

freq = 20 kHz

1.0E−5

1.0E−6

MAXIMUM REVERSE CURRENT (AMPS)

1.0E−7

VR, REVERSE VOLTAGE (VOLTS)

Figure 15. Maximum Reverse Current

1.8

1.6

1.4

1.2 1

0.8

0.6

Ipk/Io = 20

0.4

0.2 0

, AVERAGE POWER DISSIPATION (WATTS)

Ipk/Io = 5

Ipk/Io = 10

0.5 1.5 2.5

IO, AVERAGE FORWARD CURRENT (AMPS)

TJ = 25°C

Ipk/Io = p

square wave dc

Figure 16. Current Derating

http://onsemi.com

Figure 17. Forward Power Dissipation

Page 6

NTHD4P02F

SOLDERING FOOTPRINT*

0.457

0.018

2.032

0.08

0.711

0.028

0.66

0.026

Figure 18. Basic

2.032

0.08

0.711

0.028

SCALE 20:1

0.635

0.025

inches

0.457

0.018

0.66

0.026

Figure 19. Style 3

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

0.254

0.010

SCALE 20:1

1.092

0.043

inches

0.178

0.007

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in Figure 18. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads.

The minimum recommended pad pattern shown in Figure 19 improves the thermal area of the drain connections (pins 5, 6) while remaining within the confines

of the basic footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.

http://onsemi.com

Page 7

NTHD4P02F

PACKAGE DIMENSIONS

ChipFET]

CASE 1206A−03

ISSUE G

8765

1234

0.05 (0.002)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL

8765

1234

AND VERTICAL SHALL NOT EXCEED 0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE.

DIMAMIN NOM MAX MIN

b 0.25 0.30 0.35 0.010 c 0.10 0.15 0.20 0.004 D 2.95 3.05 3.10 0.116 E 1.55 1.65 1.70 0.061 e 0.65 BSC

e1 0.55 BSC

L 0.28 0.35 0.42 0.011

STYLE 3:

PIN 1. A

MILLIMETERS

1.00 1.05 1.10 0.039

1.80 1.90 2.00 0.071 0.075 0.079

5° NOM

2. A

3. S

4. G

5. D

6. D

7. C

8. C

INCHES

NOM MAX

0.041 0.043

0.012 0.014

0.006 0.008

0.120 0.122

0.065 0.067

0.025 BSC

0.022 BSC

0.014 0.017

5° NOM

ChipFET is a trademark of Vishay Siliconix.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your local Sales Representative.

NTHD4P02F/D