Datasheet nthd4n02f-d Datasheet

Page 1
NTHD4N02F
l l
s
Brochure, BRD8011/D.
Power MOSFET and Schottky Diode
20 V, 3.9 A, N−Channel, with 3.7 A Schottky Barrier Diode, ChipFETt
Features
• Leadless SMD Package Featuring a MOSFET and Schottky Diode
• 40% Smaller than TSOP−6 Package with Better Thermals
• Super Low Gate Charge MOSFET
• Ultra Low V
Schottky
F
• Pb−Free Package is Available
Applications
• Fast Switching, low Gate Charge for DC−to−DC Buck and Boost
Converters
• Li−Ion Battery Applications in Cell Phones, PDAs, DSCs,
and Media Players
• Load Side Switching
MOSFET MAXIMUM RATINGS (T
Parameter Symbol Value Unit
Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain
Current
Pulsed Drain Current Power Dissipation
Continuous Source Current (Body Diode) I Operating Junction and Storage
Temperature Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Steady
State
t v 5 s T
tp=10 ms
Steady
State
t v 5 s T
SCHOTTKY DIODE MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Peak Repetitive Reverse Voltage V DC Blocking Voltage V Average Rectified
Forward Current
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 8
Steady
State
t v 5 s 3.7 A
= 25°C unless otherwise noted)
J
DSS
GS
I
TJ, T
I
D
DM
P
D
S
T
L
RRM
R
I
F
STG
−55 to 150 °C
T
= 25°C
J
T
= 85°C 2.1
J
= 25°C 3.9
J
T
= 25°C
J
T
= 85°C 0.36
J
= 25°C 2.1
J
T
= 25°C
J
20 V
±12 V
2.9
12 A
0.91
2.6 A
260 °C
20 V 20 V
2.2 A
A
W
1 Publication Order Number:
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MOSFET
(BR)DSS
20 V
TYP
DS(on)
60 mW @ 4.5 V 80 mW @ 2.5 V
ID MAXV
3.9 A
R
SCHOTTKY DIODE
VR MAX IF MAXVF TYP
20 V
D
G
1
N−Channel MOSFET
PIN CONNECTIONS
1
A
2
A
S
3
G
C2 = Specific Device Code M = Month Code G = Pb−Free Package
0.35 V
1
S
1
SCHOTTKY DIODE
ChipFET]
CASE 1206A
STYLE 3
3.7 A
A
C
MARKING DIAGRAM
8
C
1
7
C
6
54
2 3
D
4
D
C2 M
G
ORDERING INFORMATION
Device Package Shipping
NTHD4N02FT1 ChipFET 3000/Tape & Ree NTHD4N02FT1G
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
ChipFET
(Pb−Free)
3000/Tape & Ree
NTHD4N02F/D
†
Page 2
NTHD4N02F
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – t v 5 s
1. Surface Mounted on FR4 Board using 1 in sq. pad size (Cu area = 1.27 in sq. [1 oz] including traces).
R
q
JA
R
q
JA
110 °C/W
60 °C/W
MOSFET ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Parameter Symbol Test Conditions Min Typ Max Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
DSS
GSS
V
GS
V
= 0 V
GS
V
= 16 V
DS
V
= 0 V, V
DS
= 0 V, I
= 250 mA
D
TJ = 25°C 1.0 TJ = 85°C 5.0
= "12 V "100 nA
GS
20 28 V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage V Drain−to−Source On−Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
V
V
GS
V V
GS GS
DS
= VDS, I
= 4.5, I = 2.5, I
= 10 V, I
= 250 mA
D
= 2.9 A 0.058 0.080
D
= 2.3 A 0.077 0.115
D
= 2.9 A 6.0 S
D
0.6 1.2 V
CHARGES AND CAPACITANCES
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q
ISS OSS RSS
G(TOT)
GS GD
V
= 0 V, f = 1.0 MHz,
GS
V
GS
V
DS
= 4.5 V, V
I
= 2.9 A
D
= 10 V
DS
= 10 V,
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time t Rise Time t Turn−Off Delay Time t Fall Time t
d(ON)
r
d(OFF)
f
V
GS
I
= 2.9 A, R
D
= 4.5 V, V
= 16 V,
DD
= 2.5 W
G
DRAIN−SOURCE DIODE CHARACTERISTICS (Note 2)
Forward Diode Voltage V Reverse Recovery Time t
SD
RR
Charge Time ta 9.0 Discharge Time tb 3.5 Reverse Recovery Charge Q
RR
SCHOTTKY DIODE ELECTRICAL CHARACTERISTICS (T
V
GS
V
= 0 V, I
GS
dIS/dt = 100 A/ms
= 25°C unless otherwise noted)
J
= 0 V, I
= 2.6 A 0.8 1.15 V
S
= 2.6 A,
S
Parameter Symbol Test Conditions Min Typ Max Units
Maximum Instantaneous Forward Voltage V
Maximum Instantaneous Reverse Current I
Non−Repetitive Peak Surge Current I
R
FSM
F
Halfwave, Single Pulse, 60 Hz 23 A
I
= 0.1 A 0.31
F
I
= 1.0 A 0.365
F
V
= 10 V 0.75
R
V
= 20 V 2.5
R
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
3. Switching characteristics are independent of operating junction temperatures.
180 300
80 130 30 50
2.6 4.0
0.6
0.7
5.0 10
9.0 18 10 20
3.0 6.0
12.5
6.0 nC
mA
W
pF
nC
ns
ns
V
mA
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2
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NTHD4N02F
8
3
R
DRAIN−TO−SOURCE RESISTANCE (
)
0
TYPICAL MOSFET PERFORMANCE CURVES (T
VGS = 5 V to 3 V
TJ = 25°C
= 25°C unless otherwise noted)
J
8
VDS ≥ 10 V
VGS = 2.4 V
2.2 V
4
2 V
1.8 V
6
4
2
DRAIN CURRENT (AMPS)
D,
I
0
0
1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
W
0.15
56632
4
1.6 V
1.4 V
78
910
ID = 2.9 A TJ = 25°C
2
DRAIN CURRENT (AMPS)
D,
I
0
0
0.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.1 TJ = 25°C
TC = −55°C
25°C
1
100°C
21.5 2.5
VGS = 2.5 V
0.1
0.07 VGS = 4.5 V
0.05
DRAIN−TO−SOURCE RESISTANCE (W)
0
DS(on),
0
16
24
35
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
0.04
17
DS(on),
R
35
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.7 ID = 2.9 A VGS = 4.5 V
100
VGS = 0 V
1.5
1.3
TJ = 100°C
10
1.1
DRAIN−TO−SOURCE
0.9
DS(on),
R
RESISTANCE (NORMALIZED)
0.7
−50 0−25 25
50 125100
75 150
TJ, JUNCTION TEMPERATURE (°C)
, LEAKAGE (nA)
DSS
I
1
24 8
610 1814
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
16
2
Figure 5. On−Resistance Variation with
Temperature
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Figure 6. Drain−to−Source Leakage Current
vs. Voltage
3
Page 4
NTHD4N02F
TYPICAL MOSFET PERFORMANCE CURVES (T
400
VDS = 0 V VGS = 0 V
C
ISS
TJ = 25°C
300
C
RSS
200
100
C, CAPACITANCE (pF)
C
OSS
0
50
VGSV
DS
510 10
15
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
100
VDD = 16 V ID = 2.9 A VGS = 4.5 V
= 25°C unless otherwise noted)
J
5
Q
4.5
T
4
3.5 3
2.5 2
Q
GS
Q
GD
1.5 1
0.5
GATE−TO−SOURCE VOLTAGE (V)
0
GS,
V
0 0.5 1 1.5 2 2.5 3
20
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
7
VGS = 0 V TJ = 25°C
6
5
ID = 2.9 A TJ = 25°C
20
16
12
8
4
0
DRAIN−TO−SOURCE VOLTAGE (V)
DS,
V
t
10
r
t
d(off)
t, TIME (ns)
t
t
f
d(on)
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
4
3
2
, SOURCE CURRENT (AMPS)
1
S
I
0
0.3
0.45
0.75
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
1.20.6 1.05
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4
Page 5
NTHD4N02F
10
I
, INSTANTANEOUS FORWARD
I
REVERSE CURRENT (AMPS)
5
10
0
0
TYPICAL SCHOTTKY PERFORMANCE CURVES (T
TJ = 150°C
1
CURRENT (AMPS)
F
0.1
0.00 0.20 VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 11. Typical Forward Voltage Figure 12. Maximum Forward Voltage
100E−3
TJ = 150°C
10E−3
TJ = 100°C
TJ = 25°C
TJ = −55°C
0.40
0.60 0.80
1
CURRENT (AMPS)
, INSTANTANEOUS FORWARD
F
I
0.1
0.00 0.20 VF, MAXIMUM INSTANTANEOUS FORWARD
100E−3
10E−3
= 25°C unless otherwise noted)
J
TJ = 150°C
TJ = 25°C
0.40 0.60 0.8
VOLTAGE (VOLTS)
TJ = 150°C
TJ = 100°C
100E−6
R,
10E−6
AVERAGE FORWARD CURRENT (AMPS)
O,
I
1E−3
3.5
3
2.5
2
1.5
1
0.5 0
25
TJ = 25°C
0
10
VR, REVERSE VOLTAGE (VOLTS)
Figure 13. Typical Reverse Current
dc
square wave
Ipk/Io = p Ipk/Io = 5
Ipk/Io = 10 Ipk/Io = 20
65 125105
45 145
TL, LEAD TEMPERATURE (°C)
85 165
freq = 20 kHz
1E−3
100E−6
MAXIMUM REVERSE CURRENT (AMPS)
10E−6
R,
I
20
0
VR, REVERSE VOLTAGE (VOLTS)
Figure 14. Maximum Reverse Current
1.4
1.2
1
0.8
0.6
0.4
0.2
, AVERAGE POWER DISSIPATION (WATTS)
FO
P
0
Ipk/Io = 10
Ipk/Io = 20
01
0.5 1.5 2.5
IO, AVERAGE FORWARD CURRENT (AMPS)
TJ = 25°C
Ipk/Io = p
Ipk/Io = 5
10
square wave dc
2
2
3.
3
Figure 15. Current Derating
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5
Figure 16. Forward Power Dissipation
Page 6
NTHD4N02F
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
e1
D
8765
H
E
1234
b
e
q
L
E
c
STYLE 3:
PIN 1. A
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
8765
1234
2. A
3. S
4. G
5. D
6. D
7. C
8. C
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE.
DIMAMIN NOM MAX MIN
b 0.25 0.30 0.35 0.010 c 0.10 0.15 0.20 0.004 D 2.95 3.05 3.10 0.116 E 1.55 1.65 1.70 0.061 e 0.65 BSC
e1 0.55 BSC
L 0.28 0.35 0.42 0.011
H
E
q
MILLIMETERS
1.00 1.05 1.10 0.039
1.80 1.90 2.00 0.071 0.075 0.079
5° NOM
INCHES
NOM MAX
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
5° NOM
0.05 (0.002)
SOLDERING FOOTPRINT*
0.457
0.018
2.032
0.08
0.635
0.025
2.032
0.08
0.711
0.028
1.092
0.043
0.178
0.007
0.457
0.018
0.66
0.026
0.711
0.028
SCALE 20:1
ǒ
inches
mm
Ǔ
0.66
0.026
0.254
0.010
SCALE 20:1
mm
ǒ
inches
Ǔ
Basic Style 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTHD4N02F/D
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