Datasheet nthd4508n-d Datasheet

NTHD4508N

y

Steady

y

Steady

Power MOSFET

20 V, 4.1 A, Dual N−Channel ChipFET

Features

• Low R

• Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6

• Excellent Thermal Capabilities Where Heat Transfer is Required

• Pb−Free Package is Available

Applications

• DC−DC Buck/Boost Converters

• Battery and Low Side Switching in Portable Equipment Such as MP3

Players, Cell Phones, DSCs and PDAs

• Level Shifting

and Fast Switching Speed

DS(on)

(BR)DSS

20 V

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TYP

R

DS(on)

60 m @ 4.5 V
80 m @ 2.5 V

D1, D

2

ID MAXV

4.1 A

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain

Current

Power Dissipation

Pulsed Drain Current t
Operating Junction and Storage Temperature TJ,

Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)

= 25°C unless otherwise noted)

J

T

= 25 °C

Stead

State

t  5 s T
Stead

State

t  5 s T

J

T

= 85 °C 2.2

J

= 25 °C 4.1

J

T

= 25 °C

J

T

= 85 °C 0.59

J

= 25 °C 2.1

J

= 10 µs I

p

P

T

DSS

GS

I

D

D

DM

STG

T

L

20 V

±12 V

3.0

1.13

12 A

−55 to
150

260 °C

A

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction−to−Ambient – Steady State
(Note 1)

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).

R

θ

JA

110 °C/W

G1, G

2

S1, S

2

N−Channel MOSFET

ChipFET

CASE 1206A

STYLE 2

PIN

CONNECTIONS

81

D

1

7

D

1

6

D

2

5

D

2

C8 = Specific Device Code
M = Month Code

S

1

2

G

1

3

S

2

4

G

2

MARKING
DIAGRAM

1
2
3
4

C8

M

8
7
6
5

ORDERING INFORMATION

Device Package Shipping

NTHD4508NT1 ChipFET 3000/Tape & Reel
NTHD4508NT1G

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

ChipFET

(Pb−Free)

3000/Tape & Reel

†

 Semiconductor Components Industries, LLC, 2004

October, 2004 − Rev. 3

1 Publication Order Number:

NTHD4508N/D

NTHD4508N

()

V

DS

= 10 V

V

GS

= 4.5 V, V

DS

= 10 V

V

GS

= 4.5 V, V

DS

= 16 V

V

GS

= 0 V, I

S

= 1.5 A

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise noted)

J

Symbol Test Conditions Min Typ Max Units

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V
Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

V

GS

V

GS

= 0 V, V

V

DS

V

GS

= 0 V, V

= 16 V, TJ = 125°C 10

DS

= 0 V, V

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage V
Drain−to−Source On−Resistance R

Forward Transconductance g

GS(TH)

DS(on)

FS

V

V

GS

V
V

GS
GS

DS

= VDS, I

= 4.5, I
= 2.5, I

= 10 V, I

CHARGES AND CAPACITANCES

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q

ISS
OSS
RSS

G(TOT)

G(TH)

GS

GD

V

= 0 V, f = 1.0 MHz,

GS

V

V

= 10 V

= 4.5 V, VD = 10 V,

I

= 3.1 A

D

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t

d(ON)

r

d(OFF)

f

V

= 4.5 V, VD = 16 V,

I

= 3.1 A, R

D

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V
Reverse Recovery Time t
Charge Time ta
Discharge Time tb
Reverse Recovery Charge Q

SD
RR

RR

V

= 0 V, I

GS

V

= 0 V, I

dIS/dt = 100 A/s

2. Pulse Test: Pulse Width  300 s, Duty Cycle  2%.

3. Switching characteristics are independent of operating junction temperatures.

= 0 V 20 V

= 16 V 1.0

DS

= 12 V 100 nA

GS

= 250 A 0.6 1.2 V

D

= 3.1 A 60 75

D

= 2.3 A 80 115

D

= 3.1 A 6.0 S

D

A

m

180

80
25

2.6 4.0

,

0.5

nC

0.6

0.7

5.0 10

= 2.5 

G

,

15 30
10 20

3.0 6.0

= 3.1 A 0.75 1.15 V

S

12.5

= 1.5 A,

,

9.0

3.5

6.0 nC

pF

ns

ns

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2

NTHD4508N

8

VGS = 5 V to 3 V
VGS = 2.4 V

2.2 V

4

2

DRAIN CURRENT (AMPS)

D,

I

0

1

0

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.15

0.10

TYPICAL PERFORMANCE CURVES (T

TJ = 25°C

2 V

1.8 V

1.6 V

1.4 V

4

56632

78

910

ID = 3.1 A
T

= 25°C

J

DRAIN CURRENT (AMPS)

D,

I

0.1

= 25°C unless otherwise noted)

J

8

VDS ≥ 10 V

6

4

2

TC = −55°C

25°C

100°C

0

0

0.5

1

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

TJ = 25°C

VGS = 2.5 V

21.5 2.5

3

0.05

DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on),

R

0

16

24

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

35

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.7
ID = 3.1 A
V

= 4.5 V

GS

1.5

1.3

1.1

DRAIN−TO−SOURCE

0.9

DS(on),

R

RESISTANCE (NORMALIZED)

0.07
VGS = 4.5 V

DRAIN−TO−SOURCE RESISTANCE ()

0.04

DS(on),

17

R

35

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100

VGS = 0 V

TJ = 100°C

10

, LEAKAGE (nA)

DSS

I

0.7

−50 0−25 25
TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

50 125100

Temperature

75 150

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1

24 8

610 1814

12

2016

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

3

NTHD4508N

TYPICAL PERFORMANCE CURVES (T

400

VDS = 0 V VGS = 0 V

C

ISS

TJ = 25°C

300

C

RSS

200

100

C, CAPACITANCE (pF)

C

OSS

0

50

VGSV

DS

510 10

15

20

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

100

VDD = 16 V
I

= 2.3 A

D

= 4.5 V

V

GS

= 25°C unless otherwise noted)

J

5

Q

G

4

3

Q

2

GS

Q

GD

1

GATE−TO−SOURCE VOLTAGE (VOLTS)

0

021

GS,

V

0.5
QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

7

VGS = 0 V
T

= 25°C

6

J

5

ID = 3.1 A
T

= 25°C

J

2.51.5

10

7.5

5.0

2.5

0

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

3

DS,

V

10

t, TIME (ns)

t

d(off)

t

d(on)

t

r

t

f

1

101

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

100

4

3

2

, SOURCE CURRENT (AMPS)

1

S

I

0

0.3

0.45

0.75

0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

1.20.6 1.05

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NTHD4508N

SOLDERING FOOTPRINTS*

0.457

0.018

2.032

0.08

0.66

0.026

2.032

0.08

0.711

0.028

0.635

0.025

0.635

0.025

0.457

0.018

0.66

0.026

Figure 11. Basic Figure 12. Style 2

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

0.254

0.010

SCALE 20:1

1.032

0.043

mm



inches

0.178

0.007



BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in
Figure 11. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.

The minimum recommended pad pattern shown in Figure
12 improves the thermal area of the drain connections (pins
5, 6, 7, 8) while remaining within the confines of the basic

footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq.
mm). This will assist the power dissipation path away from
the device (through the copper lead−frame) and into the
board and exterior chassis (if applicable) for the single
device. The addition of a further copper area and/or the
addition of vias to other board layers will enhance the
performance still further.

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NTHD4508N

PACKAGE DIMENSIONS

ChipFET

CASE 1206A−03

ISSUE E

A

8765

BS

1234

L

D

G

C

M

J

0.05 (0.002)

K

8765

1234

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED

0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.

7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.

DIM MIN MAX MIN MAX

A 2.95 3.10 0.116 0.122
B 1.55 1.70 0.061 0.067
C 1.00 1.10 0.039 0.043
D 0.25 0.35 0.010 0.014
G 0.65 BSC 0.025 BSC
J 0.10 0.20 0.004 0.008
K 0.28 0.42 0.011 0.017
L 0.55 BSC 0.022 BSC
M °5 NOM

°5 NOM

S 1.80

INCHESMILLIMETERS

2.00 0.072 0.080

ChipFET is a trademark of Vishay Siliconix.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD4508N/D

6