Datasheet nthd4502n-d Datasheet

NTHD4502N

y

y

Power MOSFET

30 V, 3.9 A, Dual N−Channel ChipFETt

Features

• Planar Technology Device Offers Low R

• Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.

Ideal Device for Applications Where Board Space is at a Premium.

• ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for

Applications Where Heat Transfer is Required.

• Pb−Free Package is Available

Applications

• DC−DC Buck or Boost Converters

• Low Side Switching

• Optimized for Battery and Low Side Switching Applications in

Computing and Portable Equipment

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain

Current (Note 1)

Power Dissipation
(Note 1)

Continuous Drain
Current (Note 2)

Power Dissipation
(Note 2)

Pulsed Drain Current
ESD Capability

(Note 3)
Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I
Lead Temperature for Soldering Purposes

(1/8” from case for 10 s)

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).

2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).

3. ESD Rating Information: HBM Class 0.

= 25°C unless otherwise noted)

J

T

= 25°C

Stead

State

t ≤ 5 s T

Steady

State

t ≤ 5 s 2.1

Stead

State

A

T

= 85°C 2.1

A

= 25°C 3.9

A

T

= 25°C

A

T

= 25°C

A

T

= 85°C 1.6

A

T

= 25°C P

A

t

= 10 ms

p

C = 100 pF,

R

= 1500 W

S

and Fast Switching Speed

DS(on)

DSS

GS

I

D

P

D

I

D

D

I

DM

ESD−

HBM

T

STG

S

T

L

30 V

±20 V

2.9

1.13 W

2.2

0.64 W

12 A

125 V

−55 to
150

2.5 A

260 °C

A

A

°C

http://onsemi.com

(BR)DSS

30 V

G1, G

2

PIN

CONNECTIONS

81

D

1

7

D

1

6

D

2

5

D

2

C5 = Specific Device Code
M = Month Code
G = Pb−Free Package

TYP

DS(on)

80 mW @ 10 V

110 mW @ 4.5 V

D1, D

2

S1, S

N−Channel MOSFET

CASE 1206A

MARKING
DIAGRAM

S

1

1

2

G

2

1

3

S

3

2

4

G

4

2

2

ChipFET

STYLE 2

C5 M

G

ID MAXV

3.9 A

8
7
6
5

R

ORDERING INFORMATION

Device Package Shipping

NTHD4502NT1 ChipFET 3000/Tape & Reel
NTHD4502NT1G

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

ChipFET

(Pb−Free)

3000/Tape & Reel

†

© Semiconductor Components Industries, LLC, 2005

November, 2005 − Rev. 5

1 Publication Order Number:

NTHD4502N/D

NTHD4502N

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction−to−Ambient – Steady State (Note 4)
Junction−to−Ambient – t ≤ 5 s (Note 4)
Junction−to−Ambient – Steady State (Note 5)

4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).

5. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq).

R

q

JA

R

q

JA

R

q

JA

110

60

195

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Conditions Min Typ Max Units

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V
Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

ON CHARACTERISTICS (Note 6)

Gate Threshold Voltage V
Drain−to−Source On−Resistance R

Forward Transconductance g

GS(TH)

DS(on)

FS

CHARGES AND CAPACITANCES

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q

ISS
OSS
RSS

ISS
OSS
RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

G(TH)

GS

GD

6. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

V

V

GS

V

GS

= 0 V, V

GS

V

= 0 V, V

DS

V

= VDS, I

GS

V

GS

V

GS

V

DS

V

= 0 V, f = 1.0 MHz,

GS

V

= 0 V, f = 1.0 MHz,

GS

V

= 10 V, V

GS

V

= 4.5 V, V

GS

= 0 V, I
= 0 V, V

= 10 V, I

= 4.5 V, I

= 15 V, I

= 250 mA

D

= 24 V 1.0 mA

DS

= 24 V, TJ = 125°C 10

DS

= "20 V "100 nA

GS

= 250 mA

D

= 2.9 A 78 85 mW

D

= 2.2 A 105 140

D

= 2.9 A 3.8 S

D

30 36 V

1.0 1.65 3.0 V

140

V

= 15 V

DS

135 250

V

= 24 V

DS

3.6 7.0

0.3

0.6

I

= 2.9 A

D

DS

= 15 V,

0.7

1.9

0.3

0.6

I

= 2.9 A

D

DS

= 24 V,

0.9

pF
53
16

pF
42 75
13 25

nC

nC

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2

NTHD4502N

ELECTRICAL CHARACTERISTICS (continued) (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Conditions Min Typ Max Units

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
Reverse Recovery Time t
Reverse Recovery Charge Q

SD

RR

RR

RR

RR

V

= 0 V, I

GS

V

= 0 V, I

GS

dIS/dt = 100 A/ms

V

= 0 V, I

GS

dIS/dt = 100 A/ms

SWITCHING CHARACTERISTICS (Note 7)

Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t

d(ON)

r

d(OFF)

f

d(ON)

r

d(OFF)

f

V

GS

I

V

GS

I

D

= 10 V, V

= 1 A, R

D

= 4.5 V, V

= 2.9 A, R

7. Switching characteristics are independent of operating junction temperatures.

= 2.5 A 0.85 1.2 V

S

= 2.9 A,

S

8.6 ns

4.0 nC

= 1.0 A,

S

8.4 ns

4.0 nC

6.5 12

DD
G

= 6 W

= 24 V,

5.4 10

14.9 25

1.8 5.0

7.8

DD

= 2.5 W

G

= 24 V,

12.6

9.6

2.8

ns

ns

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3

NTHD4502N

10

6

R

DRAIN−TO−SOURCE RESISTANCE (

)

6

0

TYPICAL PERFORMANCE CURVES

4 V

3.8 V

3.6 V

3.4 V

3.2 V
3 V

2.8 V

2.6 V

5

632

8

6

4

DRAIN CURRENT (AMPS)

2

D,

I

0

0

1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS = 10, 6, 5, 4.5 & 4.2 V resp.

TJ = 25°C

4

Figure 1. On−Region Characteristics

W

0.3

0.25

0.2

0.15

0.1

0.05

DS(on),

0

310

2

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

57

46

ID = 2.9 A
TJ = 25°C

89

6

VDS ≥ 10 V

5

4

3

2

DRAIN CURRENT (AMPS)

D,

I

0.12

0.11

0.10

0.09

0.08

DRAIN−TO−SOURCE RESISTANCE (W)

0.07

DS(on),

R

1

0

25°C

1

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = 25°C

2

100°C

TJ = −55°C

2

3

45

Figure 2. Transfer Characteristics

VGS = 4.5 V

VGS = 10 V

35

ID, DRAIN CURRENT (AMPS)

4

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.8
ID = 2.9 A

VGS = 10 V

1.6

1.4

1.2

DRAIN−TO−SOURCE

1.0

DS(on),

0.8

R

RESISTANCE (NORMALIZED)

0.6

−50 0−25 25

50 125100

75 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

1000

VGS = 0 V

100

10

, LEAKAGE (nA)

DSS

I

1

0.1
5

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

10

TJ = 150°C

TJ = 100°C

15

20

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

25

3

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4

NTHD4502N

TYPICAL PERFORMANCE CURVES

300

VDS = 0 V

C

ISS

VGS = 0 V

TJ = 25°C

200

C

RSS

100

C, CAPACITANCE (pF)

C

OSS

0

50

VGSV

DS

510 10

15

20 25

30

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

100

t

10

d(off)

t

d(on)

t

r

12

Q

10

V

8

DS

G

6

4

Q

GS

Q

GD

2

GATE−TO−SOURCE VOLTAGE (VOLTS)

0

021

GS,

V

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

3

VGS = 0 V
TJ = 25°C

2

V

GS

ID = 2.9 A
TJ = 25°C

3

24

20

16

12

8

4

0

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

4

DS,

V

t, TIME (ns)

1

t

f

0.1
101

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

VDD = 24 V
ID = 1.0 A
VGS = 10 V

100

1

, SOURCE CURRENT (AMPS)

S

I

0

0.3

0.4

0.6

0.7

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

0.9

10.5 0.8

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5

NTHD4502N

PACKAGE DIMENSIONS

ChipFET]

CASE 1206A−03

ISSUE G

e1

D

8765

H

E

1234

b

e

q

L

E

c

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

A

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL

8765

1234

AND VERTICAL SHALL NOT EXCEED 0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.

DIMAMIN NOM MAX MIN

b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC

e1 0.55 BSC

L 0.28 0.35 0.42 0.011

H

E

q

MILLIMETERS

1.00 1.05 1.10 0.039

1.80 1.90 2.00 0.071 0.075 0.079

5° NOM

INCHES

NOM MAX

0.041 0.043

0.012 0.014

0.006 0.008

0.120 0.122

0.065 0.067

0.025 BSC

0.022 BSC

0.014 0.017

5° NOM

0.05 (0.002)

SOLDERING FOOTPRINT*

0.457

0.018

2.032

0.08

0.635

0.025

0.635

0.025

2.032

0.08

1.092

0.043

0.178

0.007

0.457

0.018

0.66

0.026

0.711

0.028

SCALE 20:1

mm

ǒ

inches

Ǔ

0.66

0.026

0.254

0.010

SCALE 20:1

ǒ

inches

mm

Basic Style 2

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ChipFET is a trademark of Vishay Siliconix.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NTHD4502N/D

Ǔ