Datasheet nthd4102p-d Datasheet

NTHD4102P

T

l

l

s

Power MOSFET

−20 V, −4.1 A, Dual P−Channel ChipFET t

Features

• Offers an Ultra Low R

• Miniature ChipFET Package 40% Smaller Footprint than TSOP−6

• Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin

Environments such as Portable Electronics

• Simplifies Circuit Design since Additional Boost Circuits for Gate

Voltages are not Required

• Operated at Standard Logic Level Gate Drive, Facilitating Future

Migration to Lower Levels using the same Basic Topology

• Pb−Free Package is Available

Applications

• Optimized for Battery and Load Management Applications in

Portable Equipment such as MP3 Players, Cell Phones, and PDAs

• Charge Control in Battery Chargers

• Buck and Boost Converters

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain

Current (Note 1)

Power Dissipation
(Note 1)

Pulsed Drain
Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I
Lead Temperature for Soldering

Purposes (1/8” from case for 10 s)

THERMAL RESISTANCE RATINGS

Junction−to−Ambient, Steady State (Note 1)
Junction−to−Ambient, t ≤ 10s (Note 1) 60

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces)

© Semiconductor Components Industries, LLC, 2005

November, 2005 − Rev. 5

J

Parameter Symbol Value Unit

Steady State

t ≤ 10 s TA = 25°C −4.1

Steady State

t ≤ 10 s 2.1

Parameter Symbol Max Unit

Solution in the ChipFET Package

DS(ON)

= 25°C unless otherwise noted)

DSS

GS

TA = 25°C
TA = 85°C −2.1

TA = 25°C

tp = 10 ms I

T

R

I

D

P

DM

STG

S

T

q

D

L

JA

−20 V

"8.0 V

−2.9

1.1

−13.8 A

−55 to
150

−1.1 A
260 °C

113 °C/W

A

W

°C

1 Publication Order Number:

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V

(BR)DSS

−20 V

S

G

1

P−Channel MOSFET

PIN

CONNECTIONS

81

D

1

7

D

1

6

D

2

5

D

2

C7 = Specific Device Code
M = Month Code
G = Pb−Free Package

R

DS(ON)

64 mW @ −4.5 V

85 mW @ −2.5 V

120 mW @ −1.8 V

1

D

1

S

1

2

G

3

S

2

4

G

TYP ID MAX

G

2

P−Channel MOSFE

ChipFET

CASE 1206A

STYLE 2

MARKING
DIAGRAM

1
2

1

3
4

2

G

S

2

C7 M

−4.1 A

D

ORDERING INFORMATION

Device Package Shipping

NTHD4102PT1

NTHD4102PT1G

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

ChipFET
ChipFET

(Pb−Free)

3000/Tape & Ree

3000/Tape & Ree

NTHD4102P/D

2

8
7
6
5

†

NTHD4102P

,

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V
Drain−to−Source Breakdown Voltage

V

(Br)DSS

(Br)DSS/TJ

VGS = 0 V, ID = −250 mA

Temperature Coefficient
Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

DSS

GSS

VGS = 0 V

VDS = −16 V

VDS = 0 V, VGS = "8.0 V "100 nA

TJ = 25°C −1.0 mA
TJ = 85°C −5.0

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage V
Gate Threshold Temperature Coefficient V
Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(ON)

VGS = V

DS, ID

= −250 mA

VGS = −4.5 V, ID = −2.9 A 64 80 mW
VGS = −2.5 V, ID = −2.2 A 85 110
VDS = −1.8 V, ID = −1.0 A 120 170

Forward Transconductance g

FS

VDS = −10 V, ID = −2.9 A 7.0 S

CHARGES, CAPACITANCES, AND GATE RESISTANCE

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q

ISS

OSS
RSS

G(TOT)

GS
GD

VGS = 0 V, f = 1.0 MHz,

VDS = −16 V

VGS = −4.5 V, VDS = −16 V,

ID = −2.6 A

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t

d(ON)

r

d(OFF)

f

VGS = −4.5 V, VDD = −16 V,

ID = −2.6 A, RG = 2.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V
Reverse Recovery Time t

SD

RR

Charge Time ta 15
Discharge Time tb 5
Reverse Recovery Charge Q

RR

VGS = 0 V, IS = −1.1 A −0.8 −1.2 V

VGS = 0 V, dIS/dt = 100 A/ms

IS = 1.0 A

2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%

3. Switching characteristics are independent of operating junction temperatures

−20 V

−0.45 −1.5 V

−15 mV/°C

2.7 mV/°C

750

pF

100

45

7.6 8.6

nC

1.3

2.6

5.5 10

ns
12 25
32 40
23 35

20 40

0.01

ns

mC

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2

NTHD4102P

10

R

DRAIN−TO−SOURCE RESISTANCE (

)

4

9

0

TYPICAL PERFORMANCE CURVES (T

9

VGS = −10 V to −2.8 V

8
7
6
5
4
3

DRAIN CURRENT (AMPS)

2

D,

−I

1
0

0

1

5

4

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

W

0.2

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02
0

23

DS(on),

−ID, DRAIN CURRENT (AMPS)

4

TJ = 25°C

−2.4 V

−1.8 V

−1.6 V

−1.4 V

632

78

VGS = −2.5 V

VGS = −4.5 V

5

6

= 25°C unless otherwise noted)

J

8
7
6
5
4
3

DRAIN CURRENT (AMPS)

2

D,

−I

1

125°C

25°C

0

0 1.512

0.5

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

1.5
VGS = −4.5 V

1.3

1.1

0.9

DRAIN−TO−SOURCE

0.7

DS(on),

R

RESISTANCE (NORMALIZED)

0.5

−50 0−25 25
TJ, JUNCTION TEMPERATURE (°C)

TJ = −55°C

2.5

50 12510075

3 3.5

15

Figure 3. On−Resistance vs. Drain Current and

Gate Voltage

10000

1000

VGS = 0 V

TJ = 125°C

Figure 4. On−Resistance Variation with

Temperature

TJ = 100°C

100

10

, LEAKAGE (nA)

DSS

−I
1

TJ = 25°C

0.1
2

38

−V

DS,

46

57

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. Drain−to−Source Leakage Current

vs. Voltage

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3

NTHD4102P

C, CAPACITANCE (pF)

)

)

TYPICAL PERFORMANCE CURVES (T

1000

900

TJ = 25°C

800
700

C

iss

600
500
400
300
200

C

100

0

0

−VGS−V

DS

C

rss

10

4

2

8

6

12 14 16 18 20

oss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Capacitance Variation

1000

VDD = −10 V
ID = −1.0 A
VGS = −4.5 V

= 25°C unless otherwise noted)

J

5

QT

4

3

Q1

Q2

2

1

ID = −2.7 A

GATE−TO−SOURCE VOLTAGE (VOLTS

0

GS,

032

−V

418

Qg, TOTAL GATE CHARGE (nC)

TJ = 25°C

65

Figure 7. Gate−to−Source and Drain−to−Source

Voltage vs. Total Gate Charge

5

VGS = 0 V
TJ = 25°C

4

, DRAIN−TO−SOURCE VOLTAGE (VOLTS

7

DS

−V

100

t

d(off)

t

t

d(on)

f

t

r

t, TIME (ns)

10

1

101

RG, GATE RESISTANCE (OHMS)

Figure 8. Resistive Switching Time Variation

vs. Gate Resistance

100

10

1

VGS = −8 V
SINGLE PULSE
TC = 25°C

0.1

, DRAIN CURRENT (AMPS)

D

−I

0.01

0.1 1 100

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

100

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

3

2

1

, SOURCE CURRENT (AMPS)

S

−I
0

0.6 0.80.7

0.9

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 9. Diode Forward Voltage vs. Current

10 ms
100 ms

1 ms
10 ms

dc

10

1.0 1.1

1.20.50.4

Figure 10. Maximum Rated Forward Biased

Safe Operating Area

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4

NTHD4102P

PACKAGE DIMENSIONS

ChipFET]

CASE 1206A−03

ISSUE G

e1

D

8765

H

E

1234

b

e

q

L

E

c

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

A

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL

8765

1234

AND VERTICAL SHALL NOT EXCEED 0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.

DIMAMIN NOM MAX MIN

b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC

e1 0.55 BSC

L 0.28 0.35 0.42 0.011

H

E

q

MILLIMETERS

1.00 1.05 1.10 0.039

1.80 1.90 2.00 0.071 0.075 0.079

5° NOM

INCHES

NOM MAX

0.041 0.043

0.012 0.014

0.006 0.008

0.120 0.122

0.065 0.067

0.025 BSC

0.022 BSC

0.014 0.017

5° NOM

0.05 (0.002)

SOLDERING FOOTPRINT*

0.457

0.018

2.032

0.08

0.635

0.025

0.635

0.025

2.032

0.08

1.092

0.043

0.66

0.026

0.457

0.018

0.711

0.028

SCALE 20:1

mm

ǒ

inches

Ǔ

0.66

0.026

0.254

0.010

Basic Style 2

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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5

SCALE 20:1

mm

ǒ

inches

0.178

0.007

Ǔ

NTHD4102P

ChipFET is a trademark of Vishay Siliconix.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD4102P/D

6