Page 1
NTHD3100C
AND PIN A
Power MOSFET
20 V, +3.9 A /−4.4 A,
Complementary ChipFETt
Features
• Complementary N−Channel and P−Channel MOSFET
• Small Size, 40% Smaller than TSOP−6 Package
• Leadless SMD Package Provides Great Thermal Characteristics
• Trench P−Channel for Low On Resistance
• Low Gate Charge N−Channel for Test Switching
• Pb−Free Packages are Available
Applications
• DC−DC Conversion Circuits
• Load Switch Applications Requiring Level Shift
• Drive Small Brushless DC Motors
• Ideal for Power Management Applications in Portable, Battery
Powered Products
MAXIMUM RATINGS (T
Parameter Symbol Value Unit
Drain−to−Source Voltage V
Gate−to−Source Voltage
N−Channel
Continuous Drain
Current (Note 1)
P−Channel
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Pulsed Drain Current
(Note 1)
Operating Junction and Storage Temperature TJ,
Source Current (Body Diode) I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 seconds)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
= 25°C unless otherwise noted)
J
DSS
T
V
I
GS
I
D
I
D
P
DM
STG
S
T
D
L
N−Ch
P−Ch "8.0
Steady
State
t ≤ 10 s TA = 25°C 3.9
Steady
State
t ≤ 10 s TA = 25°C −4.4
Steady
State
t ≤ 5 s 3.1
N−Ch
P−Ch
TA = 25°C
TA = 85°C 2.1
TA = 25°C
TA = 85°C −2.3
TA = 25°C
t = 10 ms
t = 10 ms
20 V
"12
2.9
−3.2
1.1
12
−13
−55 to
150
2.5 A
260 °C
V
A
A
W
A
°C
http://onsemi.com
(BR)DSS
N−Channel
20 V
P−Channel
−20 V
D
1
G
1
N−Channel MOSFET
1
PIN
CONNECTIONS
8
D
1
7
D
1
6
D
2
D
2
C9 = Specific Device Code
M = Month Code
G = Pb−Free Package
Typ
DS(on)
58 mW @ 4.5 V
77 mW @ 2.5 V
64 mW @ −4.5 V
85 mW @ −2.5 V
G
2
S
1
8
1
S
1
1
2
3
45
2
G
1
S
3
2
4
G
2
P−Channel MOSFET
ID MAXV
3.9 A
−4.4 A
S
2
D
ChipFET
CASE 1206A
STYLE 2
MARKING
DIAGRAM
C9 M
G
2
R
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
8
7
6
5
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 3
1 Publication Order Number:
NTHD3100C/D
Page 2
NTHD3100C
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient − Steady State (Note 2)
Junction−to−Ambient − t ≤ 10 s (Note 2)
2. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
R
q
JA
R
q
JA
113 °C/W
60 °C/W
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Parameter Symbol N/P Test Conditions Min Typ Max Unit
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage V
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
DSS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage V
Drain−to−Source On Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
CHARGES AND CAPACITANCES
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Gate Charge Q
Gate−to−Drain “Miller” Charge Q
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
3. Pulse Test: pulse width v 250 ms, duty cycle v 2%.
N
P
VGS = 0 V
ID = 250 mA
ID = −250 mA
N VGS = 0 V, VDS = 16 V
P VGS = 0 V, VDS = −16 V −1.0
TJ = 25 °C
N VGS = 0 V, VDS = 16 V
P VGS = 0 V, VDS = −16 V −5.0
TJ = 125 °C
20
−20
1.0 mA
5.0
N VDS = 0 V, VGS = ±12 V ±100
P VDS = 0 V, VGS = ±8.0 V ±100
N
VGS = V
P
DS
ID = 250 mA
ID = −250 mA
0.6 1.2
−.45 −1.5
N VGS = 4.5 V , ID = 2.9 A 58 80
P VGS = −4.5 V , ID = −3.2 A 64 80
N VGS = 2.5 V , ID = 2.3 A 77 115
P VGS = −2.5 V, ID = −2.2 A 85 110
N VDS = 10 V, ID = 2.9 A 6.0
P VDS = −10 V , ID = −3.2 A 8.0
N
VDS = 10 V 165
P VDS = −10 V 680
N VDS = 10 V 80
f = 1 MHz, VGS = 0 V
P VDS = −10 V 100
N VDS = 10 V 25
P VDS = −10 V 70
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 2.3
P VGS = −4.5 V, VDS = −10 V, ID = −3.2 A 7.4
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.2
P VGS = −4.5 V, VDS = −10 V, ID = −3.2 A 0.6
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.4
P VGS = −4.5 V, VDS = −10 V, ID = −3.2 A 1.4
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.7
P VGS = −4.5 V, VDS = −10 V, ID = −3.2 A 2.5
V
nA
V
mW
S
pF
nC
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2
Page 3
NTHD3100C
ELECTRICAL CHARACTERISTICS (continued) (T
= 25°C unless otherwise noted)
J
Parameter Symbol N/P Test Conditions Min Typ Max Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t
d(ON)
r
d(OFF)
f
d(ON)
r
d(OFF)
f
N
VGS = 4.5 V, VDD = 10 V,
ID = 2.9 A, RG = 2.5 W
P
VGS = −4.5 V, VDD = −10 V,
ID = −3.2 A, RG = 2.5 W
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage V
Reverse Recovery Time t
SD
RR
N
VGS = 0 V, TJ = 25 °C
P IS = −2.5 A −0.8 −1.2
N
P IS = −1.5 A 13.5
Charge Time t
Discharge Time t
a
b
N IS = 1.5 A 9.0
P IS = −1.5 A 9.5
N IS = 1.5 A 3.5
VGS = 0 V,
dIS / dt = 100 A/ms
P IS = −1.5 A 4.0
Reverse Recovery Charge Q
RR
N IS = 1.5 A 6.0
P IS = −1.5 A 6.5
4. Switching characteristics are independent of operating junction temperatures.
6.3
10.7
9.6
1.5
5.8
11.7
16
12.4
IS = 2.5 A 0.8 1.15
IS = 1.5 A 12.5
ns
V
ns
nC
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3
Page 4
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
8
4
2
DRAIN CURRENT (AMPS)
D,
I
0
0
VGS = 5 V to 3 V
VGS = 2.4 V
2.2 V
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
0.15
0.1
0.05
TJ = 25°C
2 V
1.8 V
1.6 V
1.4 V
56632
4
78
910
8
VDS ≥ 10 V
6
4
2
DRAIN CURRENT (AMPS)
D,
I
0
0
0.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TC = −55°C
25°C
1
100°C
21.5 2.5
3
Figure 2. Transfer Characteristics
0.1
ID = 2.9 A
TJ = 25°C
0.07
TJ = 25°C
VGS = 2.5 V
VGS = 4.5 V
DRAIN−TO−SOURCE RESISTANCE (W)
DS(on),
R
0
0
16
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
24
35
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.7
ID = 2.9 A
VGS = 4.5 V
1.5
1.3
1.1
DRAIN−TO−SOURCE
0.9
DS(on),
R
RESISTANCE (NORMALIZED)
0.7
−50 0−25 25
TJ, JUNCTION TEMPERATURE (°C)
50 125100
75 150
Figure 5. On−Resistance Variation with
Temperature
DRAIN−TO−SOURCE RESISTANCE (W)
0.04
17
DS(on),
R
35
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100
VGS = 0 V
TJ = 100°C
10
, LEAKAGE (nA)
DSS
I
1
24 8
610 1814
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
2016
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
Page 5
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
400
VDS = 0 V VGS = 0 V
C
ISS
TJ = 25°C
300
C
RSS
200
100
C, CAPACITANCE (pF)
C
OSS
0
50
VGSV
DS
510 10
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
100
VDS = 10 V
ID = 2.9 A
VGS = 4.5 V
t
10
t, TIME (ns)
t
d(off)
t
d(on)
r
5
Q
G
4
V
DS
V
GS
3
Q
GS
Q
GD
2
1
ID = 2.9 A
TJ = 25°C
GATE−TO−SOURCE VOLTAGE (VOLTS)
0
0 0.5 1 1.5 2 2.5 3
GS,
V
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
5
VGS = 0 V
TJ = 25°C
4
3
2
15
12
9
6
3
0
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS,
V
t
1
f
101
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
100
1
, SOURCE CURRENT (AMPS)
S
I
0
0.3
0.4
0.5 0.8
0.7
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
0.9
1.00.6
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5
Page 6
NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
9
8
7
6
5
4
DRAIN CURRENT (AMPS)
2
D,
−I
1
0
0
−2.6 V
1
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. On−Region Characteristics
0.2
0.175
0.15
0.125
VGS = −5 V to −3.6 V
VGS = −3 V
53632
4
−2.4 V
−2.2 V
−2 V
−1.8 V
−1.6 V
−1.4 V
78
TJ = 25°C
910
ID = −3.2 A
TJ = 25°C
9
VDS ≥ −10 V
8
7
6
5
4
3
DRAIN CURRENT (AMPS)
2
D,
−I
1
0
0.5
0 3.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TC = −55°C
25°C
1
100°C
21.5 2.5
Figure 12. Transfer Characteristics
0.2
TJ = 25°C
0.175
0.15
0.125
VGS = −2.5 V
3
0.1
0.075
DRAIN−TO−SOURCE RESISTANCE (W)
0.05
16
DS(on),
R
24
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
35
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
1.4
ID = −3.2 A
VGS = −4.5 V
1.3
1.2
1.1
1
DRAIN−TO−SOURCE
0.9
DS(on),
R
RESISTANCE (NORMALIZED)
0.8
0.7
−50 0−25 25
−TJ, JUNCTION TEMPERATURE (°C)
50 125100
75 150
0.1
0.075
DRAIN−TO−SOURCE RESISTANCE (W)
0.05
2345
DS(on),
R
−ID, DRAIN CURRENT (AMPS)
VGS = −4.5 V
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
1000
VGS = 0 V
TJ = 100°C
100
, LEAKAGE (A)
DSS
−I
10
24 8
610 1814
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
678
12
2016
Figure 15. On−Resistance Variation with
Temperature
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Figure 16. Drain−to−Source Leakage Current
vs. Voltage
6
Page 7
1500
1200
NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VGS = 0 V
C
iss
TJ = 25°C
QT
4
−V
DS
−V
5
10
8
GS
900
VDS = 0 V
600
C
rss
C, CAPACITANCE (pF)
300
C
oss
0
50
−V
GS
−V
DS
510
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 17. Capacitance Variation
1000
VDS = −10 V
ID = −3.2 A
VGS = −4.5 V
100
t, TIME (ns)
10
t
d(off)
t
f
t
r
t
d(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
3
Q
gs
2
Q
gd
1
GATE−TO−SOURCE VOLTAGE (V)
GS,
0
−V
02468
ID = −3.2 A
TJ = 25°C
6
4
2
DRAIN−TO−SOURCE VOLTAGE (V)
DS,
0
−V
Qg, TOTAL GATE CHARGE (nC)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
5
VGS = 0 V
TJ = 25°C
4
3
2
1
, SOURCE CURRENT (AMPS)
S
−I
0
0.90.60.3
1.2
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 20. Diode Forward Voltage vs. Current
DEVICE ORDERING INFORMATION
Device Package Shipping
NTHD3100CT1 ChipFET 3000 / Tape & Reel
NTHD3100CT1G ChipFET
3000 / Tape & Reel
(Pb−Free)
NTHD3100CT3 ChipFET 10000 / Tape & Reel
NTHD3100CT3G ChipFET
10000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
http://onsemi.com
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Page 8
e1
NTHD3100C
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
D
8765
H
E
1234
b
e
q
L
E
c
A
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
0.05 (0.002)
SOLDERING FOOTPRINT*
2.032
0.08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
8765
1234
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
DIMAMIN NOM MAX MIN
b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC
e1 0.55 BSC
L 0.28 0.35 0.42 0.011
H
E
q
MILLIMETERS
1.00 1.05 1.10 0.039
1.80 1.90 2.00 0.071 0.075 0.079
5° NOM
INCHES
NOM MAX
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
5° NOM
0.635
0.025
1.092
0.043
0.178
0.007
0.457
0.018
0.254
0.66
0.010
0.026
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NTHD3100C/D
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