Datasheet nthc5513 Datasheet

NTHC5513

C

)

S

S

Power MOSFET

20 V, +3.9 A / −3.0 A,
Complementary ChipFET

Features

• Complementary N−Channel and P−Channel MOSFET

• Small Size, 40% Smaller than TSOP−6 Package

• Leadless SMD Package Featuring Complementary Pair

• ChipFET Package Provides Great Thermal Characteristics Similar to

Larger Packages

• Low R

• Low Profile (< 1.10 mm) Allows Placement in Extremely Thin

Environments Such as Portable Electronics

• Pb−Free Package is Available

Applications

• Load Switch Applications Requiring Level Shift

• DC−DC Conversion Circuits

• Drive Small Brushless DC Motors

• Designed for Power Management Applications in Portable, Battery

Powered Products

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain

urrent (Note 1

Pulsed Drain Current
(Note 1)

Power Dissipation
(Note 1)

Operating Junction and Storage
Temperature

Lead Temperature for Soldering Purposes
(1/8” from case for 10 seconds)

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).

in a ChipFET Package for High Efficiency Performance

DS(on)

= 25°C unless otherwise noted)

J

Parameter

N−Ch

teady

State
t  5 TA = 25°C 3.9

P−Ch

teady

State

t  5 TA = 25°C −3.0
N−Ch t = 10 s
P−Ch t = 10 s −9.0

Steady

State

t  5 TA = 25°C 2.1

TA = 25°C
TA = 85°C 2.1

TA = 25°C
TA = 85°C −1.6

TA = 25°C

Symbol Value Unit

20 V

±12 V

2.9

−2.2

12

1.1

−55 to
150

260 °C

T

DSS

I

I

I

DM

P

TJ,

STG

T

GS

D

D

D

L

A

A

A

W

°C

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(BR)DSS

N−Channel

20 V

P−Channel

−20 V

G

1

N−Channel MOSFET

60 m @ 4.5 V

80 m @ 2.5 V
130 m @ −4.5 V
200 m @ −2.5 V

D

1

S

PIN

CONNECTIONS

8

D

1

7

D

1

6

D

2

D

2

1

2

3

45

C1 = Specific Device Code
M = Month Code

DS(on)

1

TYP

G

2

P−Channel MOSFET

CASE 1206A

S

1

1

2

G

1

S

3

2

4

G

2

ID MAXV

−3.0 A

S

2

ChipFET

STYLE 2

MARKING
DIAGRAM

C1

M

3.9 A

D

2

8
7
6
5

R

ORDERING INFORMATION

Device Package Shipping

NTHC5513T1 ChipFET 3000/Tape & Reel

NTHC5513T1G

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

ChipFET

(Pb−Free)

3000/Tape & Reel

†

 Semiconductor Components Industries, LLC, 2004

October, 2004 − Rev. 4

1 Publication Order Number:

NTHC5513/D

NTHC5513

()

()

()

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction−to−Ambient (Note 1)

Steady State

t  5

TA = 25°C

2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).

R



JA

110

60

°C/W

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise noted)

J

Symbol N/P Test Conditions Min Typ Max Unit

OFF CHARACTERISTICS (Note 3)

Drain−to−Source Breakdown Voltage

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

V

(BR)DSS

DSS

GSS

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

V

GS(TH)

Drain−to−Source On Resistance RDS(on)

Forward Transconductance g

FS

CHARGES AND CAPACITANCES

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate−to−Source Gate Charge Q

Gate−to−Drain “Miller” Charge Q

C

ISS

OSS

RSS

G(TOT)

GS

GD

3. Pulse Test: Pulse Width  250 s, Duty Cycle  2%.

N
P

VGS = 0 V

ID = 250 A 20

ID = −250 A −20
N VGS = 0 V, VDS = 16 V 1.0
P VGS = 0 V, VDS = −16 V −1.0
N VGS = 0 V, VDS = 16 V, TJ = 85 °C 5
P VGS = 0 V, VDS = −16 V, TJ = 85 °C −5

VDS = 0 V, VGS = ±12 V ±100 nA

N

VGS = V

P

DS

ID = 250 A 0.6 1.2

ID = −250 A −0.6 −1.2
N VGS = 4.5 V , ID = 2.9 A 0.058 0.080
P VGS = −4.5 V , ID = −2.2 A 0.130 0.155
N VGS = 2.5 V , ID = 2.3 A 0.077 0.115
P VGS = −2.5 V, ID = −1.7 A 0.200 0.240
N VDS = 10 V, ID = 2.9A 6.0
P VDS = −10 V , ID = −2.2 A 6.0

N VDS = 10 V 180
P VDS = −10 V 185
N

f = 1 MHz, VGS = 0 V

P

VDS = 10 V 80

VDS = −10 V 95
N VDS = 10 V 25
P VDS = −10 V 30
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 2.6 4.0
P VGS = −4.5 V, VDS = −10 V, ID = −2.2 A 3.0 6.0
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.6
P VGS = −4.5 V, VDS = −10 V, ID = −2.2 A 0.5
N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.7

VGS = −4.5 V, VDS = −10 V, ID = −2.2 A

P

0.9

V

A

V



S

pF

nC

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NTHC5513

N

V

DD

V

GS

I

D

V

DD

−16 V, V

GS

I

D

V

GS

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise noted)

J

Symbol N/P Test Conditions Min Typ Max Unit

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
Fall Time t
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t

t

d(ON)

r

d(OFF)

f

d(ON)

r

d(OFF)

f

N

P

V

= 16 V, V

= 16 V,

VDD = −16 V, V

=

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage (Note 5)

Reverse Recovery Time (Note 4) t

V

SD

RR

N
P

VGS = 0 V

N IS = 1.5 A 12.5
P IS = −1.5 A 32

Charge Time t

Discharge Time t

a

b

N IS = 1.5 A 9.0
P
N

V

= 0 V,

= 0 V,

dIS / dt = 100 A/s

P IS = −1.5 A 22

Reverse Recovery Charge Q

RR

N IS = 1.5 A 6.0
P

4. Switching characteristics are independent of operating junction temperatures.

5. Pulse Test: Pulse Width  250 s, Duty Cycle  2%.

= 4.5 V, I

= 4.5 V,

= 2.9 A,

= 2.9 A,

RG = 2.5 

= −4.5 V, ID = −2.2 A,

= −4.5 V,

= −2.2 A,

RG = 2.5 

IS = 2.6 A 0.8 1.15

IS = −2.1 A −0.8 −1.15

IS = −1.5 A 10

IS = 1.5 A 3.5

IS = −1.5 A

5.0 10

9.0 18
10 20

3.0 6.0

7.0 12
13 25
33 50
27 40

15

ns

V

ns

nC

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NTHC5513

TYPICAL N−CHANNEL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

8

VGS = 5 V to 3 V
VGS = 2.4 V

2.2 V

4

2

DRAIN CURRENT (AMPS)

D,

I

0

0

1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.15

0.1

0.05

TJ = 25°C

VDS ≥ 10 V

2 V

6

8

1.8 V

1.6 V

1.4 V

4

2

DRAIN CURRENT (AMPS)

D,

I

TC = −55°C

25°C

100°C

0

4

56632

78

910

0

0.5

1

21.5 2.5

3

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0.1

ID = 2.7 A
T

= 25°C

J

0.07

TJ = 25°C

VGS = 2.5 V

VGS = 4.5 V

DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on),

R

0

16

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

24

35

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.7
ID = 2.7 A
V

= 4.5 V

GS

1.5

1.3

1.1

DRAIN−TO−SOURCE

0.9

DS(on),

R

RESISTANCE (NORMALIZED)

0.7

−50 0−25 25

75 150

50 125100

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

DRAIN−TO−SOURCE RESISTANCE ()

0.04

DS(on),

17

R

35

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100

VGS = 0 V

TJ = 100°C

10

, LEAKAGE (nA)

DSS

I

1

24 8

610 1814

12

2016

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

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NTHC5513

TYPICAL N−CHANNEL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

400

VDS = 0 V VGS = 0 V

C

ISS

TJ = 25°C

300

C

RSS

200

100

C, CAPACITANCE (pF)

C

OSS

0

50

VGSV

DS

510 10

15

20

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

100

VDD = 16 V
I

= 2.7 A

D

= 4.5 V

V

GS

t

t

d(OFF

t

d(ON)

r

)

t

f

10

t, TIME (ns)

1

101

100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

5

4.5

Q

G

4

3.5
3

2.5
2

Q

1.5

GS

1

0.5

GATE−TO−SOURCE VOLTAGE (VOLTS)

0

0 0.5 1 1.5 2 2.5 3

GS,

V

Q

GD

QG, TOTAL GATE CHARGE (nC)

ID = 2.7 A
T

= 25°C

J

Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

7

VGS = 0 V
T

= 25°C

6

J

5

4

3

2

, SOURCE CURRENT (AMPS)

1

S

I

0

0.3

0.45

0.75

0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

20

16

12

8

4

0

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS,

V

1.20.6 1.05

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NTHC5513

TYPICAL P−CHANNEL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

4

VGS = −6 V to −3 V
VGS = −2.4 V

TJ = 25°C

−2 V

4

VDS ≥ −10 V

−2.2 V

3

3

−1.8 V

2

2

−1.6 V

1

DRAIN CURRENT (AMPS)

D,

−I
0

0

1

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. On−Region Characteristics

0.5

0.4

1

DRAIN CURRENT (AMPS)

−1.4 V

−1.2 V

D,

−I
0

4

5

632

78

0.5

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.25

ID = −2.1 A
T

= 25°C

J

TJ = 25°C

0.225

TC = −55°C

25°C

100°C

1

Figure 12. Transfer Characteristics

VGS = −2.5 V

0.2

0.3

0.175

0.2

0.15

VGS = −4.5 V

0.1

DRAIN−TO−SOURCE RESISTANCE ()

0

16

DS(on),

R

24

35

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.125

DRAIN−TO−SOURCE RESISTANCE ()

0.1

0.5 1.5 2.5 3.5

DS(on),

R

−ID, DRAIN CURRENT (AMPS)

21.5 2.5

3

Figure 13. On−Resistance vs. Gate−to−Source

Voltage

1.6
ID = −2.1 A

= −4.5 V

V

GS

1.4

1.2

1

DRAIN−TO−SOURCE

0.8

DS(on),

R

RESISTANCE (NORMALIZED)

0.6

−50 0−25 25

75 150

50 125100

−TJ, JUNCTION TEMPERATURE (°C)

Figure 15. On−Resistance Variation with

Temperature

10000

1000

, LEAKAGE (A)

100

DSS

−I

10

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Figure 14. On−Resistance vs. Drain Current

and Gate Voltage

VGS = 0 V

TJ = 150°C

TJ = 100°C

24 8

610 1814

12

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 16. Drain−to−Source Leakage Current

vs. Voltage

2016

600

500

VDS = 0 V VGS = 0 V

C

ISS

NTHC5513

TYPICAL P−CHANNEL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

5

TJ = 25°C

−V

DS

4

Q

T

−V

GS

15

12

400

C

RSS

300

200

C, CAPACITANCE (pF)

C

100

OSS

0

50

−V

GS

−V

DS

510 10

15

20

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 17. Capacitance Variation

1000

100

t

d(OFF)

t

f

t, TIME (ns)

10

t

d(ON)

t

r

VDD = −16 V
I

= −2.1 A

D

= −4.5 V

V

GS

1

1 10 100

R

, GATE RESISTANCE (OHMS)

G

Figure 19. Resistive Switching Time Variation

vs. Gate Resistance

3

Q

2

1

GATE−TO−SOURCE VOLTAGE (V)

GS,

0

−V

GS

Q

GD

ID = −2.1 A
T

= 25°C

J

9

6

3

0

DRAIN−TO−SOURCE VOLTAGE (V)

DS,

−V

01234

QG, TOTAL GATE CHARGE (nC)

Figure 18. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

2.5

1.5

0.5

, SOURCE CURRENT (AMPS)

S

−I

VGS = 0 V
T

= 25°C

J

2

1

0

0.3

0.70.5

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

0.9

Figure 20. Diode Forward Voltage vs. Current

2
1

Duty Cycle = 0.5

0.2

0.1

0.1

0.05

0.02

Thermal Impedance

Normalized Effective Transient

0.01

−4 −3 −2 −1

10 1010

Single Pulse

TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

10 1 10 100 600

Square Wave Pulse Duration (sec)

Figure 21. Thermal Response

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Notes:

P

DM

t

1

1. Duty Cycle, D =

2. Per Unit Base = R
TA = PDMZ

3. T

JM −

4. Surface Mounted



t
t
t

2

1
2

thJA

JA

= 90°C/W

(t)

NTHC5513

SOLDERING FOOTPRINT*

0.457

0.018

2.032

0.08

0.711

0.028

0.66

0.026

Figure 22. Basic

0.635

0.025

0.635

0.025

0.457

0.018

0.66

0.026

Figure 23. Style 2

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

2.032

0.08

1.092

0.043

0.178

0.007

0.254

0.010

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in
Figure 22. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.

The minimum recommended pad pattern shown in
Figure 23 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the

confines of the basic footprint. The drain copper area is

0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.

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NTHC5513

PACKAGE DIMENSIONS

ChipFET

CASE 1206A−03

ISSUE E

A

8765

BS

1234

L

D

G

C

M

J

0.05 (0.002)

K

8765

1234

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED

0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.

6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.

7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.

DIM MIN MAX MIN MAX

A 2.95 3.10 0.116 0.122
B 1.55 1.70 0.061 0.067
C 1.00 1.10 0.039 0.043
D 0.25 0.35 0.010 0.014
G 0.65 BSC 0.025 BSC

J 0.10 0.20 0.004 0.008

K 0.28 0.42 0.011 0.017

L 0.55 BSC 0.022 BSC

M °5 NOM

°5 NOM

S 1.80

INCHESMILLIMETERS

2.00 0.072 0.080

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NTHC5513

ChipFET is a trademark of Vishay Siliconix.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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