Datasheet ntgd4161p-d Datasheet

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NTGD4161P

Power MOSFET

−30 V, −2.3 A, Dual P−Channel, TSOP−6

Features

• Fast Switching Speed

• Low Gate Charge

• Low R

• Independently Connected Devices to Provide Design Flexibility

• This is a Pb−Free Device

Applications

• Load Switch

• Battery Protection

• Portable Devices Like PDAs, Cellular Phones and Hard Drives

DS(on)

(BR)DSS

−30 V

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P−Channel (MOSFET1)

MaxV

DS(on)

160 mW @ −10 V

280 mW @ −4.5 V

P−Channel

(MOSFET2)

MAXIMUM RATINGS (T

Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain

Current (Note 1)

Power Dissipation (Note 1)

Continuous Drain Current (Note 2)

Power Dissipation (Note 2) TA = 25°C P Pulsed Drain Current Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I Lead Temperature for Soldering Purposes

(1/8” from case for 10 s)

= 25°C unless otherwise noted)

Parameter Symbol Value Unit

−30 V ±20 V

−2.1

1.1

−1.5

0.6 W

−10 A

−55 to 150

−0.8 A 260 °C

°C

DSS

Steady State

t ≤ 5 s TA = 25°C −2.3 Steady

State t ≤ 5 s 1.3

Steady State

TA = 25°C TA = 85°C −1.5

TA = 25°C P

TA = 25°C TA = 85°C −1.1

tp =10 ms

STG

THERMAL RESISTANCE RATINGS

Parameter Symbol Max Unit

Junction−to−Ambient − Steady State (Note 1) Junction−to−Ambient − Steady State (Note 2) 225 Junction−to−Ambient − t ≤ 5 s (Note 1) 95 Junction−to−Case − Steady State (Note 1)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using 1 in. pad size (Cu. area = 1.2 in2 [1 oz] including traces)

2. When surface mounted to an FR4 board using minimum recommended pad size (Cu. area = 0.047 in2)

115

°C/W

MARKING DIAGRAM

D1G1S1S2D2

TSOP−6

CASE 318G

STYLE 13

S8 = Specific Device Code M = Date Code* G = Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation may vary depending upon

manufacturing location.

S8 MG

ORDERING INFORMATION

Device Package Shipping

NTGD4161PT1G TSOP−6

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

3000 / Tape & Ree

†

September, 2006 − Rev. 1

1 Publication Order Number:

NTGD4161P/D

Page 2

NTGD4161P

ELECTRICAL CHARACTERISTICS (T

=25°C unless otherwise stated)

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V Drain−to−Source Breakdown Voltage

Temperature Coefficient

(BR)DSS/TJ

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

= 0 V, I

= 0 V,

= −24 V

= 0 V, V

= −250 mA

= ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V Gate Threshold Temperature

Coefficient

GS(TH)/TJ

Drain−to−Source On Resistance R

Forward Transconductance g

GS(TH)

DS(on)

= VDS, ID = −250 mA

= −10 V, I

= −4.5 V, I

= −5.0 V, I

= −2.1 A 105 160

= −1.6 A 190 280

= −2.1 A 2.7 S

CHARGES AND CAPACITANCES

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Threshold Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q

ISS OSS RSS

G(TOT)

G(TH)

= −15 V, f = 1.0 MHz,

= −10 V, V

= −2.1A

= 0 V

= −5.0 V,

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t Rise Time t Turn−Off Delay Time t Fall Time t

d(on)

d(off)

= −4.5 V, V

= −1.0 A, R

= −15 V,

= 6.0 Ω

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

Reverse Recovery Time t Charge Time t Discharge Time t Reverse Recovery Charge Q

a b

= 0 V,

= −0.8 A

= 0 V, dIS/dt = 100 A/ms,

= −0.8 A

3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

−30 V 22 mV/°C

= 25°C −1.0 mA

= 125°C −10

−1.0 −1.9 −3.0 V

−4.7 mV/°C

281

50 28

5.6 7.1

0.65

1.2

0.90

7.6 14

9.2 23

12.5 20

4.5 12

= 25°C −0.79 −1.2

= 125°C −0.65

8.0

5.7

2.3 3 nC

mΩ

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NTGD4161P

, DRAIN−TO−SOURCE RESISTANCE

, DRAIN−TO−SOURCE RESISTANCE (

)

TYPICAL PERFORMANCE CURVES

−10 V

, DRAIN CURRENT (A)

−I

01234

−VDS, DRAIN−TO−SOURCE VOLTAGE (V)

−4.5 V

Figure 1. On−Region Characteristics

0.5

0.4

0.3

0.2 TJ = 25°C

0.1

3456

DS(on)

TJ = 125°C

810

−VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 3. On−Resistance versus

Gate−to−Source Voltage

TJ = 25°C

−3.8 V

−3.6 V

−3.4 V

−3.2 V

−2.8 V

ID = −2.1 A

−4 V

−3 V

, DRAIN CURRENT (A)

−I

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

, DRAIN−TO−SOURCE RESISTANCE (W)

01234 6

DS(on)

Figure 4. On−Resistance versus Drain Current

VDS ≥ −3 V

150°C

25°C

−40°C

234

−VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 2. Transfer Characteristics

TJ = 25°C

VGS = −4.5 V

VGS = −10 V

−ID, DRAIN CURRENT (A)

and Temperature

0.3

0.2

0.1

0.0

DS(on)

−50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C)

ID = −1.6 A VGS = −4.5 V

ID = −2.1 A VGS = −10 V

Figure 5. On−Resistance Variation with

Temperature

1000

100

, LEAKAGE(nA)

DSS

−I

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VGS = 0 V

TJ = 150°C

TJ = 125°C

0 5 10 15 20 25 3

−VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 6. On−Resistance Variation with

Temperature

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NTGD4161P

1.0

, EFFECTIVE TRANSIENT THERMAL

TYPICAL PERFORMANCE CURVES

350

300

250

200

150

100

C, CAPACITANCE (pF)

RSS

0 5 10 15 20 25

DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

0.8 VGS = 0 V

0.7

0.6

0.5

0.4

TJ = 150°C

TJ = 25°C VGS = 0 V

ISS

OSS

, GATE−TO−SOURCE VOLTAGE (V)

−V 012345

ID = −2.1 A TJ = 25°C

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−to−Source and

Drain−to−Source Voltage versus Total Charge

100

VGS = −10 V Single Pulse TA = 25°C

100 ms 1 ms

−V

, DRAIN−TO−SOURCE VOLTAGE (V)

0.3

, SOURCE CURRENT (A)

0.2

−I

0.1 0

0.3 0.4 0.6 0.8 0.9 1.0

−VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 9. Diode Forward Voltage versus

TJ = 125°C

0.70.5

Current

TJ = 25°C

TJ = −40°C

, DRAIN CURRENT (A)

0.1

−I

DS(on)

Limit Thermal Limit Package Limit

0.01

0.1 1 10 100

−VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 10. Maximum Rated Forward Biased

Safe Operating Area

0.5

0.2

0.1

0.05

0.02

0.01

RESPONSE (NORMALIZED)

0.001

1E−06 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+0

Single Pulse

1E−05 1E−04

t, time (s)

Figure 11. FET Thermal Response

10 ms

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Page 5

0.05 (0.002)

NTGD4161P

PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE S

456

SOLDERING FOOTPRINT*

2.4

0.094

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.

DIMAMIN NOM MAX MIN

A1 0.01 0.06 0.10 0.001

b 0.25 0.38 0.50 0.010 c 0.10 0.18 0.26 0.004 D 2.90 3.00 3.10 0.114 E 1.30 1.50 1.70 0.051 e 0.85 0.95 1.05 0.034 L 0.20 0.40 0.60 0.008

MILLIMETERS

0.90 1.00 1.10 0.035

2.50 2.75 3.00 0.099 0.108 0.118 0° 10° 0° 10°

− −

STYLE 13:

PIN 1. GATE 1

2. SOURCE 2

3. GATE 2

4. DRAIN 2

5. SOURCE 1

6. DRAIN 1

INCHES

NOM MAX

0.039 0.043

0.002 0.004

0.014 0.020

0.007 0.010

0.118 0.122

0.059 0.067

0.037 0.041

0.016 0.024

0.95

0.037

1.9

0.075

0.95

0.037

0.7

0.028

1.0

0.039

SCALE 10:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTGD4161P/D