Datasheet ntd85n02r-d Datasheet

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Page 1

NTD85N02R

Power MOSFET 24 Volts, 85 Amps Single N−Channel, DPAK/IPAK

Features

• Planar HD3e Process for Fast Switching Performance

• Low R

• Low Capacitance to Minimize Driver Losses

• Low Gate Charge to Minimize Switching Losses

• Pb−Free Packages are Available

Applications

• CPU Power Delivery

• DC−DC Converters

• Low Side Switching

MAXIMUM RATINGS (T

Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain

Current R (Note 1)

Power Dissipation R

(Note 1)



Continuous Drain Current R (Note 2)

Power Dissipation R

(Note 2)



Continuous Drain Current R (Note 1)

Power Dissipation R

(Note 1)



Pulsed Drain Current

Current Limited by Package TA = 25°C I Operating Junction and Storage

Temperature Source Current (Body Diode) I Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain−to−Source Avalanche

Energy TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 13 Apk, L = 1.0 mH, RG = 25 

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter Symbol Value Unit

DSS



Steady

State

TA = 25°C, t

TA = 25°C TA = 85°C 12 TA = 25°C P

TA = 25°C TA = 85°C 8.8 TA = 25°C P

TC = 25°C TC = 85°C 58 TC = 25°C P

= 10s

DmaxPkg

TJ,

STG

EAS 85 mJ

24 V

±20 V

2.4 W

1.25 W

78.1 W

192 A

45 A

−55 to +150

78 A

260 °C

°C

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(BR)DSS

24 V 5.2 m  V85 A

DPAK

CASE 369AA

STYLE2

MAX ID MAX

DS(ON)

N−Channel

DPAK−3

CASE 369D

STYLE 2

MARKING DIAGRAM

& PIN ASSIGNMENTS

1 Gate 2 Drain 3 Source 4 Drain

YWW85N02G

132

YWW

85 N02G

Y = Year WW = Work Week 85N02R = Specific Device Code G = Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

January, 2007 − Rev. 9

1 Publication Order Number:

NTD85N02R/D

Page 2

NTD85N02R

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain) Junction−to−TAB (Drain) Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.



JC−TAB



1.6

3.5 52

100

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V Drain−to−Source Breakdown Voltage

Temperature Coefficient Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 A

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V Negative Threshold Temperature

Coefficient Drain−to−Source on Resistance R

GS(TH)

GS(TH)/TJ

DS(ON)

VGS = VDS, ID = 250 A

VGS = 10 V ID = 20 A 4.8 5.2

VGS = 4.5 V ID = 20 A 6.5

Forward Transconductance g

VDS = 10 V, ID = 15 A 38 S

CHARGES AND CAPACITANCES

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Threshold Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q Total Gate Charge Q

ISS OSS RSS

G(TOT)

G(TH)

GS GD

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 20 V

VGS = 5.0 V, VDS = 10 V; ID = 10 A

VGS = 10 V, VDS = 10 V;

ID = 10 A

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t Rise Time t Turn−Off Delay Time t Fall Time t

d(ON)

d(OFF)

VGS = 10 V, VDS = 10 V,

ID = 30 A, RG = 3.0 

3. Pulse Test: pulse width v 300 s, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

24 28 V

20.5

TJ = 25 °C 1.5

TJ = 125°C 10

1.0 1.5 2.0 V 4

2050

871 359

17.7

1.6

2.6

7.1

35.1 nC

6.3 77 25 12

mV/°C

A

mV/°C

m

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Page 3

NTD85N02R

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

Reverse Recovery Time t Charge Time t Discharge Time t Reverse Recovery Charge Q

a b

VGS = 0 V,

IS = 30 A

VGS = 0 V, dIS/dt = 100 A/s,

IS = 20 A

TJ = 25°C 0.81 1.0

TJ = 125°C 0.65

37.5

16.8

20.7 27 nC

PACKAGE PARASITIC VALUES

Source Inductance L Drain Inductance, DPAK L Drain Inductance, IPAK* L Gate Inductance L Gate Resistance R

S D D G

TA = 25°C

2.49

0.0164

1.88

3.46

1.2



*Assume standoff of 110 mils.

ORDERING INFORMATION

Device Package Shipping

NTD85N02R DPAK NTD85N02RG DPAK

75 Units / Rail

(Pb−Free) NTD85N02R−001 IPAK NTD85N02R−1G IPAK

800 / Tape & Reel

(Pb−Free) NTD85N02RT4 DPAK NTD85N02RT4G DPAK

2500 / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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Page 4

NTD85N02R

160

10 V

120

, DRAIN CURRENT (AMPS)

010

4.4 V 5 V

6 V

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS = 4 V

3.8 V

3.6 V

3.4 V

3.2 V 3 V

2.8 V

2.6 V

2.4 V

160

VDS ≥ 10 V

120

, DRAIN CURRENT (AMPS)

TJ = 25°C

TJ = 125°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.018 VGS = 10 V

0.014

0.010

0.018

0.014

0.010

VGS = 4.5 V

TJ = 125°C

0.006

, DRAIN−TO−SOURCE RESISTANCE ()

0.002

DS(on)

ID, DRAIN CURRENT (AMPS)

TJ = 25°C

TJ = −55°C

Figure 3. On−Resistance versus Drain Current

and Temperature

1.8 ID = 40 A

1.6

1.4

1.2

1.0

(NORMALIZED)

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

−50 50250−25 75 125100

= 10 V

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

120 160

150

0.006

, DRAIN−TO−SOURCE RESISTANCE ()

0.002 0

DS(on)

Figure 4. On−Resistance versus Drain Current

100,000

10,000

, LEAKAGE (nA)

1000

DSS

100

VGS = 0 V

01510 2

Figure 6. Drain−to−Source Leakage Current

TJ = 25°C

TJ = −55°C

40 ID, DRAIN CURRENT (AMPS)

120

and Temperature

TJ = 150°C

TJ = 125°C

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

versus Voltage

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Page 5

4800

)

4000

3200

2400

NTD85N02R

POWER MOSFET SWITCHING

TJ = 25°C

iss

rss

iss

1600

C, CAPACITANCE (pF)

800

10 0 10 15 20

VGS = 0 VVDS = 0 V

oss

rss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

100

t, TIME (ns)

1 10 100

d(off)

d(on)

RG, GATE RESISTANCE (OHMS)

VDS = 10 V ID = 40 A VGS = 10 V

ID = 10 A TJ = 25°C

, GATE−TO−SOURCE VOLTAGE (VOLTS

QG, TOTAL GATE CHARGE (nC)

1248

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

VGS = 0 V

70 60 50 40 30 20

, SOURCE CURRENT (AMPS)

0.2 0.4 1

0.6 0.8

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

TJ = 25°C

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

1000

100

VGS = 20 V SINGLE PULSE TC = 25°C

, DRAIN CURRENT (AMPS)

0.1

0.1 1 10010 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Figure 10. Diode Forward Voltage versus Current

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

Safe Operating Area

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10 s

100 s

1 ms

10 ms dc

Page 6

Normalized to R

(NORMALIZED)

0.1

, EFFECTIVE TRANSIENT THERMAL RESISTANCE

r(t)

0.01

0.00001 0.0001

at Steady State



NTD85N02R

0.001 0.01 0.1 1 10 t, TIME (s)

Figure 12. Thermal Response

Normalized to R

at Steady State,



1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board

(NORMALIZED)

0.1

, EFFECTIVE TRANSIENT THERMAL RESPONSE

r(t)

0.01

0.00001 0.0001

0.001 0.01 0.1 1 10 100 1000 t, TIME (s)

Figure 13. Thermal Response

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Page 7

NTD85N02R

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE A

NOTES:

SEATING

−T−

PLANE

123

2 PL

0.13 (0.005) T

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.025 0.035 0.63 0.89 E 0.018 0.024 0.46 0.61 F 0.030 0.045 0.77 1.14 H 0.386 0.410 9.80 10.40 J 0.018 0.023 0.46 0.58 L 0.090 BSC 2.29 BSC R 0.180 0.215 4.57 5.45 S 0.024 0.040 0.60 1.01 U 0.020 −−− 0.51 −−− V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

SOLDERING FOOTPRINT*

6.20

0.244

5.80

0.228

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

2.58

0.101

3.0

0.118

0.063

1.6

SCALE 3:1

6.172

0.243

inches

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Page 8

NTD85N02R

PACKAGE DIMENSIONS

DPAK−3

CASE 369D−01

ISSUE B

−T−

SEATING PLANE

B R

123

D 3 PL

0.13 (0.005) T

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD85N02R/D