Datasheet ntd78n03r-d Datasheet

NTD78N03R

Power MOSFET

25 V, 85 A, Single N−Channel, DPAK

Features

• Low R

• Optimized Gate Charge to Minimize Switching Losses

• Pb−Free Packages are Available

to Minimize Conduction Losses

DS(on)

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Applications

• VCORE Applications

• DC−DC Converters

• Optimized for Low Side Switching

MAXIMUM RATINGS (T

Parameter

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current (R

Power Dissipation (R

q

JA

Continuous Drain Current (R

Power Dissipation (R

q

JA

Continuous Drain Current (R

Power Dissipation (R

q

JC

Pulsed Drain Current

Current Limited by Package TA = 25°C I

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 8.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy (V L = 5.0 mH, I

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

) (Note 1)

q

JA

) (Note 1)

) (Note 2)

q

JA

) (Note 2)

)

q

JC

)

= 24 V, VGS = 10 V,

DD

(pk) = 5.5 A, RG = 25 W)

L

= 25°C unless otherwise noted)

J

Symbol Value Unit

DSS

GS

I

D

I

D

I

D

I

DM

DmaxPkg

stg

S

E

AS

T

L

Steady

State

TA = 25°C

TA = 85°C 11.4

TA = 25°C P

TA = 25°C

TA = 85°C 8.8

TA = 25°C P

TC = 25°C

TC = 85°C 66

TC = 25°C P

tp = 10 ms

25 V

"20 V

14.7

2.3 W

11.3

1.4 W

85

76.9 W

98 A

32 A

−55 to 175

77 A

75 mJ

260 °C

A

°C

(BR)DSS

25 V

G

2

1

3

CASE 369C

DPAK

(Bend Lead)

STYLE 2

DS(on)

5.0 @ 11.5 V

7.5 @ 4.5 V

D

4

1

2

CASE 369D

DPAK

(Straight Lead)

STYLE 2

TYP

S

4

3

ID MAXV

85 A

N−Channel

4

1

2

3

CASE 369AC

3 IPAK

(Straight Lead)

R

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

4

Drain

YWW78N03RG

Gate

3

2

1

Source

Drain

Y = Year WW = Work Week 78N03R= Device Code G = Pb−Free Package

1

Gate

2

Drain

3 Source

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.

August, 2006 − Rev. 4

1 Publication Order Number:

NTD78N03R/D

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Ambient − Steady State (Note 3)

Junction−to−Ambient − Steady State (Note 4)

NTD78N03R

R

q

JC

R

q

JA

R

q

JA

1.95

65

110

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

V

(BR)DSS

V

(BR)DSS/TJ

VGS = 0 V, ID = 250 mA

25 V

10 mV/°C

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

DSS

GSS

VGS = 0 V,

= 20 V

V

DS

VDS = 0 V, VGS = "20 V "100 nA

TJ = 25°C 1.5 mA

TJ = 125°C 10

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

V

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS =

10V to 11.5 V

VGS = 4.5 V

ID = 30 A 5.0 5.8 mW

ID = 15 A 4.9 5.7

ID = 30 A 7.5 9.0

1.0 1.7 3.0 V

−5.3 mV/°C

ID = 15 A 7.2 8.5

Forward Transconductance gFS VDS = 15 V, ID = 10 A 23 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

C

iss

oss

rss

G(TOT)

G(TH)

GS

GD

VGS = 0 V, f = 1.0 MHz,

= 12 V

V

DS

VGS = 4.5 V, VDS = 20 V,

= 20 A

I

D

1794

882

373

19.4 24

0.8

2.9

12.4

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time

t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

r

d(off)

f

VGS = 4.5 V, VDS = 20 V,

I

= 20 A, R

D

= 2.5 W

G

11

75

18

17

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

V

SD

RR

Charge Time ta 16.5

Discharge Time tb 22

Reverse Recovery Time Q

RR

VGS = 0 V,

= 30 A

I

S

TJ = 25°C 0.8 1.0 V

VGS = 0 V, dIs/dt = 100 A/ms,

= 20 A

I

S

38

31 nC

3. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.

4. Surface−mounted on FR4 board using the minimum recommended pad size.

5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

6. Switching characteristics are independent of operating junction temperatures.

pF

nC

ns

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2

NTD78N03R

120

100

80

10 V

6 V

4.5 V

60

40

, DRAIN CURRENT (AMPS)

20

D

I

0

0864

19753

2

V

, DRAIN−TO−SOURCE VOLTAGE (V)

DS

Figure 1. On−Region Characteristics

11.50

10.25

9.00

TJ = 25°C

VGS = 4 V

3.5 V

2.6 V

2.4 V

ID = 30 A T

= 25°C

J

3 V

10

120

VDS ≥ 10 V

100

80

60

40

TJ = 125°C

, DRAIN CURRENT (AMPS)

20

D

I

TJ = 25°C

TJ = −55°C

0

03 8

21

, GATE−TO−SOURCE VOLTAGE (V)

V

GS

45

67

Figure 2. Transfer Characteristics

0.01 TJ = 25°C

0.008

VGS = 4.5 V

7.75

6.50

5.25

, DRAIN−TO−SOURCE RESISTANCE (mΩ)

4.00

DS(on)

R

3

48910

VGS, GATE−TO−SOURCE VOLTAGE (V)

75

6

Figure 3. On−Resistance versus

Gate−to−Source Voltage

2

ID = 30 A V

1.8

1.6

1.4

1.2

(NORMALIZED)

1

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

−50 100750−25 125 175

R

= 10 V

GS

to 11.5V

5025

TJ, JUNCTION TEMPERATURE (°C)

150

0.006

VGS = 10 V

0.004

, DRAIN−TO−SOURCE RESISTANCE (Ω)

0.002

DS(on)

R

10

15 20 25 30

ID, DRAIN CURRENT (A)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

100000

10000

, LEAKAGE (nA)

DSS

I

VGS = 0 V

TJ = 175°C

1000

TJ = 100°C

100

2181614 20

4681012

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 5. On−Resistance Variation with

Temperature

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Figure 6. Drain−To−Source Leakage

Current versus Voltage

3

3500

3000

VDS = 0 V

C

iss

VGS = 0 V

TJ = 25°C

2500

2000

C

1500

1000

C, CAPACITANCE (pF)

rss

C

iss

C

oss

500

C

0

10 5 0 5 10152025

1520

VGSV

DS

rss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

NTD78N03R

5

4

V

3

2

1

, GATE−TO−SOURCE VOLTAGE (V)

GS

0

V

04812

Drain−to−Source Voltage versus Total Charge

Q

T

DS

Q

1

Q

, TOTAL GATE CHARGE (nC)

g

Q

2

Figure 8. Gate−to−Source and

V

GS

ID = 20 A T

= 25°C

J

16 20

V

20

DS

, DRAIN−TO−SOURCE VOLTAGE (V)

16

12

8

4

0

1000

VDS = 15 V I

= 20 A

D

= 4.5 V

V

GS

100

t

t, TIME (ns)

10

r

t

f

t

d(off)

t

d(on)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

40

VGS = 0 V

35

T

= 25°C

J

30

25

20

15

10

, SOURCE CURRENT (AMPS)

5

S

I

0

0.3 0.6 0.9 1.2 VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage versus Current

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4

NTD78N03R

ORDERING INFORMATION

Order Number Package Shipping

NTD78N03R DPAK

NTD78N03RG DPAK

(Pb−Free)

NTD78N03RT4 DPAK

NTD78N03RT4G DPAK

(Pb−Free)

NTD78N03R−1 DPAK Straight Lead

NTD78N03R−1G DPAK Straight Lead

(Pb−Free)

NTD78N03R−35 DPAK Straight Lead

(3.5 " 0.15 mm)

NTD78N03R−35G DPAK Straight Lead

(3.5 " 0.15 mm)

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

75 Units/Rail

2500 Tape & Reel

75 Units/Rail

†

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5

NTD78N03R

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE O

NOTES:

SEATING

−T−

PLANE

B

V

S

R

4

A

123

K

F

L

D

2 PL

G

0.13 (0.005) T

C

E

Z

U

J

H

M

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14 G 0.180 BSC 4.58 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.102 0.114 2.60 2.89 L 0.090 BSC 2.29 BSC R 0.180 0.215 4.57 5.45 S 0.025 0.040 0.63 1.01 U 0.020 −−− 0.51 −−− V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

MILLIMETERSINCHES

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

5.80

0.228

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

3.0

0.118

0.063

1.6

SCALE 3:1

6.172

0.243

ǒ

inches

mm

Ǔ

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6

V

S

−T−

SEATING PLANE

F

B

R

4

123

G

A

K

J

3 PL

D

0.13 (0.005) T

NTD78N03R

PACKAGE DIMENSIONS

DPAK

CASE 369D−01

ISSUE B

NOTES:

C

E

Z

H

M

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G

H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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7

SEATING PLANE

NTD78N03R

PACKAGE DIMENSIONS

3 IPAK, STRAIGHT LEAD

CASE 369AC−01

ISSUE O

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

B

V

R

C

E

A

W

F

G

K

J

H

D

3 PL

0.13 (0.005) W

2.. CONTROLLING DIMENSION: INCH.

3. SEATING PLANE IS ON TOP OF DAMBAR POSITION.

4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.043 0.94 1.09 G 0.090 BSC 2.29 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27

W 0.000 0.010 0.000 0.25

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD78N03R/D

8