N--Channel Power MOSFET
100 V, 23 A, 56 mΩ, Logic
Level
Features
Low R
100% Avalanche Tested
AEC--Q101 Qualified
These Devices are Pb--Free, Halogen Free/BFR Free and are RoHS
MAXIMUM RATINGS (T
Drain--to--Source VoltageV
Gate--to--Source Voltage -- ContinuousV
Continuous Drain
Current
Power DissipationSteady
Pulsed Drain Current
Operating and Storage Temperature RangeTJ,T
Source Current (Body Diode)I
Single Pulse Drain --to--Source Avalanche
Energy (V
23 A, L = 0.3 mH, R
Lead Temperature for Soldering
Purposes, 1/8 from Case for 10 Seconds
DS(on)
Compliant
DD
=25C unless otherwise noted)
J
Parameter
Steady
State
State
=50Vdc,VGS=10Vdc,I
=25Ω)
G
TC=25C
TC= 100C16
TC=25CP
tp=10ms
L(pk)
SymbolValueUnit
stg
100V
±20V
23
83W
80A
-- 5 5 t o
+175
23A
79mJ
260C
DSS
GS
I
D
D
I
DM
S
E
AS
=
T
L
A
C
V
(BR)DSS
100 V
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R
56 m Ω @4.5V
52 m Ω @10V
G
CASE 369AA
MAXIDMAX
DS(on)
D
S
2
1
3
DPAK
STYLE 2
23 A
4
THERMAL RESISTANCE RATINGS
ParameterSymbolMaxUnit
Junction--to--Case (Drain) -- Steady State
Junction--to--Ambient -- Steady State (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu A rea 1.127 sq in [2 oz] including traces).
Semiconductor Components Industries, LLC, 2010
March, 2010 -- Rev. 0
R
θ
JC
R
θ
JA
C/W
1.8
39
1Publication Order Number:
MARKING DIAGRAM
& PIN ASSIGNMENT
4Drain
YWW
6415AN
LG
1
Gate
Drain
6415ANL = Device Code
Y= Year
WW= Work Week
G= Pb--Free Package
3
2
Source
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
3. Switching characteristics are independent of operating junction temperatures.
100
92
115mV/C
TJ=25C1.0
TJ= 125C100
1.02.0V
4.8mV/C
4456
1024
156
70
20
1.1
3.1
14
11
91
40
71
TJ=25C0.871.2
TJ= 125C0.74
64
40
24
152nC
V
mA
mΩ
S
pF
nC
ns
V
ns
ORDERING INFORMATION
DevicePackageShipping
NTD6415ANLT4GDPAK
2500 / Tape & Reel
(Pb--Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification B rochure, BRD8011/D.
†
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2
Page 3
NTD6415ANL
, DRAIN CURRENT (A)
D
I
45
40
35
30
VGS=10V
5V
4V
TJ=25C
3.6 V
3.4 V
25
20
15
10
3.2 V
3.0 V
2.8 V
5
0
012345
, DRAIN--TO--SOURCE VOLTAGE (V)
V
DS
Figure 1. On --Region Characteristics
0.050
0.048
0.046
0.044
ID=23A
T
=25C
J
45
VDS≥ 10 V
40
35
30
25
20
TJ=25C
TJ=--55C
, DRAIN CURRENT (A)
D
I
15
10
TJ= 125C
5
0
1234
VGS, GATE--TO--SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
0.050
0.048
0.046
0.044
TJ=25C
VGS=4.5V
0.042
, DRAIN--TO--SOURCE RESISTANCE (Ω)
0.040
R
DS(on)
2345678910
, GATE--TO--SOURCE VOLTAGE (V)
V
GS
Figure 3. On--Region versus Gate Voltage
3.0
ID=23A
V
=4.5V
2.5
GS
2.0
1.5
(NORMALIZED)
1.0
, DRAIN--TO--SOURCE RESISTANCE
DS(on)
0.5
R
--50--250255075100 125 150 175
, J UNCTION TEMPERATURE (C)
T
J
Figure 5. On --Resistance Variation with
Temperature
VGS=10V
0.042
, DRAIN--TO--SOURCE RESISTANCE (Ω)
0.040
DS(on)
5 10152025
R
, DRAIN CURRENT (A)
I
D
Figure 4. On--Resistance versus Drain
Current and Gate Voltage
10000
VGS=0V
TJ= 150C
1000
, LEAKAGE (nA)
DSS
I
100
102030405060708090 100
TJ= 125C
VDS, DRAIN--TO--SOURCE VOLTAGE (V)
Figure 6. Drain--to--Source Leakage Current
versus Voltage
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3
Page 4
NTD6415ANL
2500
TJ=25C
V
2000
GS
1500
C
1000
C, CAPACITANCE (pF)
500
C
rss
iss
C
oss
0
0 102030405060708090100
, DRAIN--TO--SOURCE VOLTAGE (V)
V
DS
Figure 7. Capacitance Variation
1000
VDS=80V
I
=23A
D
V
=4.5V
GS
t
r
t
f
t
d(off)
t
d(on)
t, TIME (ns)
100
10
=0V
10
Q
T
8
6
Q
ds
, GATE--TO--SOURCE VOLTAGE (V)
V
GS
4
2
0
Q
gs
VDS=80V
I
T
05101520253035
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate--to-- Source Voltage and
Drain--to-- Source Voltage versus Total Charge
25
TJ=25C
V
=0V
GS
20
15
10
, S OURCE CURRENT (A)
5
S
I
=23A
D
=25C
J
1
110100
R
, G ATE RESISTANCE (Ω)
G
Figure 9. Resistive Switching Time Variation
100
10
VGS=10V
SINGLE PULSE
T
C
1
, DRAIN CURRENT (A)
D
I
0.1
1101001000
versus Gate Resistance
=25C
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
V
, DRAIN--TO--SOURCE VOLTAGE (V)
DS
10 ms
100 ms
1ms
10 ms
dc
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95
VSD, SOURCE --TO--DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
125
100
75
50
25
AVALANCHE ENERGY (mJ)
0
255075100125150175
TJ, S TARTING JUNCTION TEMPERATURE
Current
ID=23A
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
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4
Page 5
NTD6415ANL
10
Duty Cycle = 0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
THERMAL RESISTANCE
0.01
(C/W) EFFECTIVE TRANSIENT
JC(t)
θ
R
0.001
SINGLE PULSE
0.0000010.000010.00010.0010.010.1110
t, PULSE TIME (s)
Figure 13. Thermal Response
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5
Page 6
NTD6415ANL
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA--01
ISSUE A
NOTES:
SEATING
-- T --
PLANE
B
V
S
R
4
123
A
H
C
E
Z
U
F
J
L
D
2PL
0.13 (0.005)T
M
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMINMAX
A 0.235 0.2455.976.22
B 0.250 0.2656.356.73
C 0.086 0.0942.192.38
D 0.025 0.0350.630.89
E 0.018 0.0240.460.61
F 0.030 0.0450.771.14
H 0.386 0.4109.80 10.40
J 0.018 0.0230.460.58
L0.090 BSC2.29 BSC
R 0.180 0.2154.575.45
S 0.024 0.0400.601.01
U 0 . 0 2 0-- -- --0 . 5 1-- -- --
V 0.035 0.0500.891.27
Z 0 . 1 5 5-- -- --3 . 9 3-- -- --
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
6.20
0.244
5.80
0.228
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor andare registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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2.58
0.101
3.0
0.118
0.063
1.6
SCALE 3:1
6.172
0.243
mm
inches
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution C enter for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA