Datasheet ntd60n02r Datasheet

Page 1
NTD60N02R
d)
4
Power MOSFET
62 A, 25 V, N−Channel, DPAK
Features
• Low R
• Low C
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• Pb−Free Packages are Available
to Minimize Conduction Loss
DS(on)
to Minimize Driver Loss
iss
(BR)DSS
25 V
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R
TYP
DS(on)
8.4 mW @ 10 V
N−Channel
D
ID MAXV
62 A
MAXIMUM RATINGS (T
Drain−to−Source Voltage V Gate−to−Source Voltage − Continuous V Thermal Resistance
Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current
Continuous @ T
Continuous @ T
Continuous @ T Thermal Resistance
Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C
Thermal Resistance
Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C
Operating and Storage Temperature TJ, and
Single Pulse Drain−to−Source Avalanche Energy
− Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10.0 Vdc, IL = 11 Apk, L = 1.0 mH, RG = 25 W)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended pad size.
= 25°C unless otherwise noted)
J
Rating Symbol Value Unit
JC D
JA D
JA D
L
25 Vdc
±20 Vdc
2.6 58
62 50 32
80
1.87
10.5
120
1.25
8.5
− 55 to 175
60 mJ
260 °C
= 25°C, Chip
C
= 25°C, Limited by Package
C
= 25°C, Limited by Wires
A
R
R
R
DSS
P
I I I
P
I
P
I
T E
T
GS
q
D D D
q
D
q
D
stg
AS
°C/W
W
A A A
C/W
W
A
°C/W
W
A
°C
G
4
2
1
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
T60
YWW
2
1
Drain
Gate
Y = Year WW = Work Week T60N02R = Device Code G = Pb−Free Package
1
CASE 369AC
3 IPAK
(Straight Lead)
N02RG
3 Source
S
4
2
3
Gate
1
2
CASE 369D
DPAK
(Straight Lea
STYLE 2
4
Drain
T60
YWW
N02RG
1
2
Drain
3 Source
3
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
See detailed ordering and shipping information in the package
ORDERING INFORMATION
dimensions section on page 5 of this data sheet.
1 Publication Order Number:
NTD60N02R/D
Page 2
NTD60N02R
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V
= 0 Vdc, ID = 250 mAdc)
GS
Temperature Coefficient (Positive) Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 3)
(VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 31 Adc)
Forward Transconductance (VDS = 10 Vdc, ID = 15 Adc) (Note 3) g
DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance C
(VDS = 20 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance C
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time Rise Time t Turn−Off Delay Time t
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 31 Adc, RG = 3.0 W)
Fall Time t Gate Charge
(VGS = 4.5 Vdc, ID = 31 Adc,
VDS = 10 Vdc) (Note 3)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 31 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 31 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge Q
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
C
t
d(on)
d(off)
Q Q Q
V
t t t
FS
iss
oss
rss
GS GD
SD
rr
a b
25
−
27.5
25.5
−
−
mV/°C
mAdc
Vdc
−
−
−
−
1.5 10
− − ±100 nAdc
Vdc
1.0
−
1.5
4.1
2.0
−
mV/°C
mW
−
−
−
11.2
8.4
8.2
12.5
10.5
−
− 27 − Mhos
− 1000 1330
pF
− 480 640
− 180 225
− 7.0 −
r
− 33 −
ns
− 19 −
f T
− 9.0 −
− 9.5 14
nC
− 2.2 −
− 5.0 −
−
−
−
− 29.1 −
0.88
1.15
0.80
1.2
−
Vdc
− ns
− 13.6 −
− 15.5 −
rr
− 0.02 −
mC
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2
Page 3
NTD60N02R
4
I
, DRAIN CURRENT (A)
R
, DRAIN−TO−SOURCE RESISTANCE (
)
R
, DRAIN−TO−SOURCE RESISTANCE
8
0
TYPICAL CHARACTERISTICS
140
120
100
80
60
40
D
20
0
W
0.05
0.04
0.03
VGS = 10 V
8.0 V
6.0 V
4.2 V
4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V2.8 V
0246810
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°C
5.0 V
4.5 V
2.6 V
2.4 V
120
100
, DRAIN CURRENT (A)
D
I
Figure 1. On−Region Characteristics
0.05
ID = 62 A TJ = 25°C
0.04
0.03
VDS w 10 V
80
60
40
TJ = 175°C
20
0
0246
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
TJ = −55°C
Figure 2. Transfer Characteristics
TJ = 25°C
0.02
0.01
0
DS(on)
2
46
VGS, GATE−TO−SOURCE VOLTAGE (V)
810
Figure 3. On−Resistance versus
2.0 ID = 31 A
VGS = 10 V
1.8
1.6
1.4
1.2
(NORMALIZED)
1.0
0.8
DS(on)
0.6
−50 −25 0 25 50 75 100 125 150
Gate−to−Source Voltage
TJ, JUNCTION TEMPERATURE (°C)
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
100000
10000
, LEAKAGE (nA)
DSS
I
175
0.02
0.01
0
20 40 60 80 100 120
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 10 V
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 175°C
1000
100
10
0 6 12 18 2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 100°C
14
Figure 5. On−Resistance Variation with
Temperature
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Figure 6. Drain−to−Source Leakage Current
versus Voltage
3
Page 4
NTD60N02R
C, CAPACITANCE (pF)
t, TIME (ns)
V , DRAIN−TO−SOURCE VOLTAGE (V)
.8
2000
C
iss
TJ = 25°C
1500
C
iss
VDS = 0 V
VGS = 0 V
1000
C
rss
C
oss
500
C
rss
0
10 5 0 5 10 15 20
V
GSVDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
VDD = 10 V ID = 31 A VGS = 10 V
100
10
t
d(off)
t
d(on)
t
r
t
f
5
Q
T
4
Q
GS
Q
DS
3
V
DS
V
GS
2
1
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
0
04610
28
ID = 31 A
TJ = 25°C
20
16
12
8
4
0
DS
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
80
VGS = 0 V
70
TJ = 25°C
60 50 40 30 20
, SOURCE CURRENT (A)
S
I
10
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
, DRAIN CURRENT (A)
D
I
R
DS(ON)
LIMIT
THERMAL LIMIT
1
PACKAGE LIMIT
0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
0
0.2 0.4 0.6 0.8 1.0 1.2
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
10 ms
100 ms
1 ms
10 ms
dc
1.4 1.6 1
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Page 5
NTD60N02R
1.0 D = 0.5
0.2
0.1
0.05
0.1
0.02
(NORMALIZED)
0.01
SINGLE PULSE
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
Figure 12. Thermal Response
ORDERING INFORMATION
Order Number Package Shipping
NTD60N02R DPAK−3 75 Units / Rail NTD60N02RG DPAK−3
NTD60N02RT4 DPAK−3 2500 / Tape & Reel NTD60N02RT4G DPAK−3
NTD60N02R−1 DPAK−3 Straight Lead 75 Units / Rail NTD60N02R−1G DPAK−3 Straight Lead
NTD60N02R−35 DPAK−3 Straight Lead
NTD60N02R−35G DPAK−3 Straight Lead
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
(3.5 ± 0.15 mm)
(3.5 ± 0.15 mm)
P
t, TIME (s)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T
− TC = P
J(pk)
2
(pk)
1
R
(t)
q
JC
1100.10.010.0010.00010.00001
†
75 Units / Rail
2500 / Tape & Reel
75 Units / Rail
75 Units / Rail
75 Units / Rail
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Page 6
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE A
NOTES:
SEATING
−T−
PLANE
B
V
S
R
4
123
A
H
C
E
Z
U
F
J
L
D
2 PL
0.13 (0.005) T
M
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.025 0.035 0.63 0.89 E 0.018 0.024 0.46 0.61 F 0.030 0.045 0.77 1.14 H 0.386 0.410 9.80 10.40 J 0.018 0.023 0.46 0.58 L 0.090 BSC 2.29 BSC R 0.180 0.215 4.57 5.45 S 0.024 0.040 0.60 1.01 U 0.020 −−− 0.51 −−− V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
6.20
0.244
5.80
0.228
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
2.58
0.101
3.0
0.118
0.063
1.6
SCALE 3:1
6.172
0.243
mm
ǒ
inches
Ǔ
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Page 7
SEATING PLANE
NTD60N02R
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
B
V
R
C
E
A
W
F
G
K
J
H
D
3 PL
0.13 (0.005) W
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE.
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.043 0.94 1.09
G 0.090 BSC 2.29 BSC
H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27
W 0.000 0.010 0.000 0.25
MILLIMETERSINCHES
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Page 8
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
V
S
−T−
SEATING PLANE
F
B R
4
123
G
A
K
D 3 PL
0.13 (0.005) T
C
E
J
H
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14
0.090 BSC 2.29 BSC
G H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTD60N02R/D
8
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