• Power Supplies Secondary Side Synchronous Rectification
DS(on)
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V
(BR)DSS
60 V24 A
R
MAX
DS(ON)
37 mW @ 10 V
N−Channel
D
MAX
I
D
(Note 1)
MAXIMUM RATINGS (T
Parameter
Drain−to−Source VoltageV
Gate−to−Source Voltage − ContinuousV
Gate−to−Source Voltage − Nonrepetitive
< 10 ms)
(T
P
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Pulsed Drain Current
Operating and Storage Temperature RangeTJ, T
Source Current (Body Diode)I
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(V
L = 0.3 mH, R
Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
(Note 1)
q
JC
= 50 Vdc, V
DD
q
JC
GS
= 25 W)
G
J
= 25°C Unless otherwise specified)
J
Steady
State
Steady
State
= 25°C
= 10 V, I
TC = 25°C
TC = 100°C16
TC = 25°CP
tp = 10 ms
= 24 A,
L(pk)
SymbolValueUnit
stg
60V
$20V
$30V
24
55W
75A
−55 to
+175
24A
86.4mJ
260°C
A
°C
V
I
E
DSS
GS
GS
I
D
D
DM
S
AS
T
L
THERMAL RESISTANCE RATINGS
ParameterSymbolMaxUnit
Junction−to−Case (Drain) Steady State
(Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [1 oz] including traces).
R
q
JC
R
q
JA
58.6
2.7
°C/W
G
S
MARKING
DIAGRAMS
4
Drain
4
2
1
3
5414N = Device Code
Y= Year
WW= Work Week
G= Pb−Free Device
DPAK
CASE 369AA
STYLE 2
Gate
1
YWW
2
Drain
5414N
3
Source
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Drain−to−Source Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain CurrentI
Gate−Body Leakage CurrentI
V
(BR)DSS
V
(BR)DSS/TJ
DSS
GSS
VDS = 0 V, ID = 250 mA
VGS = 0 V
V
= 60 V
DS
VDS = 0 V, VGS = $20 V$100nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Negative Threshold Temperature CoefficientV
Drain−to−Source On−VoltageV
V
GS(th)
GS(th)/TJ
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V, ID = 24 A0.71.16
VGS = 10 V, ID = 12 A, 150°C0.7
Drain−to−Source On−ResistanceR
Forward Transconductanceg
DS(on)
FS
VGS = 10 V, ID = 24 A28.437
VDS = 15 V, ID = 20 A24S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output CapacitanceC
Transfer CapacitanceC
Total Gate ChargeQ
Threshold Gate ChargeQ
Gate−to−Source ChargeQ
Gate−to−Drain ChargeQ
C
iss
oss
rss
G(TOT)
G(TH)
GS
GD
VDS = 25 V, VGS = 0 V,
f = 1 MHz
VGS = 10 V, VDS = 48 V,
I
= 24 A
D
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3)
Turn−On Delay Time
t
Rise Timet
Turn−Off Delay Timet
Fall Timet
d(on)
r
d(off)
f
VGS = 10 V, VDD = 48 V,
= 24 A, RG = 9.1 W
I
D
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 2)
Reverse Recovery Timet
Charge Timet
Discharge Timet
Reverse Recovery Stored ChargeQ
V
SD
rr
a
b
RR
VGS = 0 V
I
= 24 A
S
IS = 24 Adc, VGS = 0 Vdc,
/dt = 100 A/ms
dI
S
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
3. Switching characteristics are independent of operating junction temperatures.
60V
67.3mV/°C
TJ = 25°C1.0mA
TJ = 150°C50
2.03.24.0V
0.74mV/°C
8001200
165
75
2548
1.1
4.8
11.3
12
58
47
69
TJ = 25°C0.921.15
TJ = 125°C0.8
45.7
31.7
14
76nC
V
mW
pF
nC
ns
V
ns
ORDERING INFORMATION
DevicePackageShipping
NTD5414NT4GDPAK
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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2
Page 3
NTD5414N
TYPICAL PERFORMANCE CURVES
40
35
30
7 V
10 V
6 V
TJ = 25°C
5.5 V
25
20
5 V
15
10
, DRAIN CURRENT (A)
D
I
5
0
4.8 V
4.5 V
VGS = 4.2 V
012345
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
Figure 1. On−Region Characteristics
0.08
0.07
0.06
0.05
ID = 24 A
T
= 25°C
J
40
VDS ≥ 10 V
35
30
25
20
15
10
, DRAIN CURRENT (A)
D
I
5
0
345 62
, GATE−TO−SOURCE VOLTAGE (V)
V
GS
Figure 2. Transfer Characteristics
0.040
TJ = 25°C
0.030
TJ = 125°C
TJ = 25°C
TJ = −55°C
VGS = 10 V
0.04
0.03
, DRAIN−TO−SOURCE RESISTANCE (W)
0.02
567 8 910
DS(on)
R
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.5
ID = 24 A
V
= 10 V
GS
2.0
1.5
(NORMALIZED)
1.0
, DRAIN−TO−SOURCE RESISTANCE
0.5
DS(on)
R
−50 −250255075100 125 150 175
, JUNCTION TEMPERATURE (°C)
T
J
Figure 5. On−Resistance Variation with
Temperature
0.020
, DRAIN−TO−SOURCE RESISTANCE (W)
0.010
DS(on)
102030401545
R
2535
I
, DRAIN CURRENT (A)
D
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1000
VGS = 0 V
TJ = 150°C
100
TJ = 125°C
, LEAKAGE (nA)
DSS
I
10
51015202530354045505560
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
Page 4
NTD5414N
TYPICAL PERFORMANCE CURVES
1500
TJ = 25°C
1000
VGS = 0 V
C
iss
500
C, CAPACITANCE (pF)
C
C
rss
0
oss
0 102030405060
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 7. Capacitance Variation
1000
100
t, TIME (ns)
10
V
DD
I
= 24 A
D
V
GS
= 48 V
= 10 V
t
f
t
d(off)
t
r
t
d(on)
10
Q
T
8
Q
1
6
Q
2
4
2
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
0510152025
Q
, TOTAL GATE CHARGE (nC)
g
Figure 8. Gate−to−Source Voltage vs. Total
Charge
25
VGS = 0 V
T
= 25°C
J
20
15
10
ID = 24 A
T
= 25°C
J
1
110100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
0 V ≤ VGS ≤ 10 V
Single Pulse
TC = 25°C
100
1 ms
100 ms
10 ms
10
, DRAIN CURRENT (A)
1
D
I
R
DS(on)
dc
Limit
Thermal Limit
0.1
0.110100
Package Limit
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
, SOURCE CURRENT (A)
5
S
I
0
0.40.50.60.70.80.91.0
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 10. Diode Forward Voltage vs. Current
90
80
ID = 24 A
70
60
50
40
30
20
AVALANCHE ENERGY (mJ)
10
0
255075100125150175
, STARTING JUNCTION TEMPERATURE (°C)
T
J
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
Page 5
NTD5414N
TYPICAL PERFORMANCE CURVES
100
D = 0.5
0.2
10
0.1
0.05
0.02
1
0.01
0.1
r(t), (°C/W)
0.01
0.001
Single Pulse
Surface−Mounted on FR4 Board using 1 sq in pad size, 1 oz Cu
0.0000010.000010.00010.0010.010.11101001000
t, PULSE TIME (s)
Figure 13. Thermal Response
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5
Page 6
NTD5414N
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE A
NOTES:
SEATING
−T−
PLANE
B
V
S
R
4
123
A
H
C
E
Z
U
F
J
L
D
2 PL
0.13 (0.005)T
M
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMIN MAX
A 0.235 0.2455.976.22
B 0.250 0.2656.356.73
C 0.086 0.0942.192.38
D 0.025 0.0350.630.89
E 0.018 0.0240.460.61
F 0.030 0.0450.771.14
H 0.386 0.4109.80 10.40
J 0.018 0.0230.460.58
L0.090 BSC2.29 BSC
R 0.180 0.2154.575.45
S 0.024 0.0400.601.01
U 0.020−−−0.51−−−
V 0.035 0.0500.891.27
Z 0.155−−− 3.93−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
6.20
0.244
5.80
0.228
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
2.58
0.101
3.0
0.118
0.063
1.6
SCALE 3:1
6.172
0.243
ǒ
inches
mm
Ǔ
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD5414N/D
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