Datasheet ntd4969n-d Datasheet

NTD4969N

Power MOSFET

30 V, 41 A, Single N−Channel, DPAK/IPAK

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• Three Package Variations for Design Flexibility

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

• CPU Power Delivery

• DC−DC Converters

to Minimize Conduction Losses

DS(on)

V

(BR)DSS

30 V

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R

MAX ID MAX

DS(ON)

9.0 mW @ 10 V

19 mW @ 4.5 V

D

41 A

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

Continuous Drain Current R (Note 2)

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Current Limited by Package TA = 25°C I

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy (T I

L

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

q

JA

(Note 1)

q

JA

q

JA

(Note 2)

q

JA

q

JC

(Note 1)

q

JC

= 25°C, VDD = 24 V, VGS = 10 V,

J

= 19 Apk, L = 0.1 mH, RG = 25 W)

= 25°C unless otherwise stated)

J

TA = 25°C

TA = 100°C 9.0

TA = 25°C P

TA = 25°C

Steady

State

tp=10ms

TA = 100°C 6.6

TA = 25°C P

TC = 25°C

TC = 100°C 29

TC = 25°C P

TA = 25°C I

DSS

GS

I

D

I

D

I

D

DM

DmaxPkg

TJ,

T

STG

S

EAS 18 mJ

T

L

30 V

±20 V

12.7

2.56 W

9.4

1.38 W

41

26.3 W

150 A

40 A

−55 to +175

24 A

260 °C

A

°C

2

1

3

CASE 369AA

DPAK

(Bent Lead)

STYLE 2

4

Drain

49

YWW

69NG

2

Drain

1

Gate

Source

G

S

N−CHANNEL MOSFET

4

1

2

3

CASE 369AC

3 IPAK

(Straight Lead)

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

49

YWW

69NG

2

1

3

Gate

Y = Year WW = Work Week 4969N = Device Code G = Pb−Free Package

Drain

3

Source

Gate

4

1

2

3

CASE 369D

IPAK

(Straight Lead

DPAK)

4

Drain

49

YWW

69NG

2

1

3

Drain

Source

April, 2011 − Rev. 1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

1 Publication Order Number:

NTD4969N/D

NTD4969N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−TAB (Drain)

Junction−to−Ambient – Steady State (Note 3)

Junction−to−Ambient – Steady State (Note 4)

3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

4. Surface−mounted on FR4 board using the minimum recommended pad size.

R

q

R

q

JC

JC−TAB

R

q

JA

R

q

JA

5.7

4.3

58.6

108.6

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

V

(BR)DSS

V

(BR)DSS

T

DSS

GSS

VGS = 0 V, ID = 250 mA

/

J

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain−to−Source On Resistance R

V

GS(TH)

V

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V

VGS = 4.5 V

Forward Transconductance g

FS

VDS = 1.5 V, ID = 30 A 36 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

C

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 15 V

VGS = 4.5 V, VDS = 15 V, ID = 30 A

VGS = 10 V, VDS = 15 V, ID = 30 A 16.5 nC

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

t

d(ON)

r

d(OFF)

f

VGS = 4.5 V, VDS = 15 V,

= 15 A, RG = 3.0 W

I

D

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

7. Assume terminal length of 110 mils.

30 V

17

TJ = 25°C 1.0

TJ = 125°C 10

1.5 1.8 2.5 V

4.5

ID = 30 A 6.9 9.0

ID = 15 A 6.9

ID = 30 A 13.6 19

ID = 15 A 13.2

837

347

180

9.0

1.42

2.8

4.8

10

27

13.3

6.4

mV/°C

mA

mV/°C

mW

pF

nC

ns

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2

NTD4969N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter UnitMaxTypMinTest ConditionSymbol

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

t

d(ON)

r

d(OFF)

f

VGS = 10 V, VDS = 15 V,

= 15 A, RG = 3.0 W

I

D

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

V

SD

RR

a

b

RR

VGS = 0 V,

I

= 30 A

S

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 30 A

PACKAGE PARASITIC VALUES

Source Inductance (Note 7)

Drain Inductance, DPAK L

Drain Inductance, IPAK (Note 7) L

Gate Inductance (Note 7) L

Gate Resistance R

L

S

D

G

TA = 25°C

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

7. Assume terminal length of 110 mils.

6.5

20.2

17.2

4.2

TJ = 25°C 0.91 1.1

TJ = 125°C 0.82

20.8

9.8

11

8.0 nC

2.85

0.0164

1.88

4.9

1.0 2.2

ns

V

ns

nH

W

ORDERING INFORMATION

Device Package Shipping

NTD4969NT4G DPAK

2500 / Tape & Reel

(Pb−Free)

NTD4969N−1G IPAK

75 Units / Rail

(Pb−Free)

NTD4969N−35G IPAK Trimmed Lead

75 Units / Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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3

NTD4969N

TYPICAL PERFORMANCE CURVES

70

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

012345

10 V thru 4.5 V

TJ = 25°C

V

, DRAIN−TO−SOURCE VOLTAGE (V)

DS

VGS = 4.2 V

3.8 V

3.4 V

3.0 V

2.6 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.019

0.018

0.017

0.016

0.015

0.014

0.013

0.012

0.011

0.010

0.009

0.008

0.007

0.006

, DRAIN−TO−SOURCE RESISTANCE (mW)

0.005

3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

DS(on)

R

VGS, GATE−TO−SOURCE VOLTAGE (V)

ID = 30 A T

= 25°C

J

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

70

VDS = 10 V

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

12345

20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5

, DRAIN−TO−SOURCE RESISTANCE (mW)

4

10 20 30 40 50 60 70

DS(on)

R

TJ = 25°C

TJ = 125°C

VGS, GATE−TO−SOURCE VOLTAGE (V)

VGS = 4.5 V

ID, DRAIN CURRENT (A)

TJ = −55°C

TJ = 25°C

VGS = 10 V

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

1.8 ID = 30 A

1.7 V

= 10 V

GS

1.6

1.5

1.4

1.3

1.2

1.1

1.0

(NORMALIZED)

0.9

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.7

0.6

DS(on)

−50 −25 0 25 50 75

R

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

100 125 175

150

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10000

1000

, LEAKAGE (nA)

100

DSS

I

10

51015202530

4

TJ = 150°C

TJ = 125°C

TJ = 85°C

VGS = 0 V

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

NTD4969N

TYPICAL PERFORMANCE CURVES

1200

1100

1000

900

C

iss

800

700 600

500

400

300

C, CAPACITANCE (pF)

C

oss

200

100

0

015

5

C

rss

10 25

20

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

1000

VDD = 15 V I

= 15 A

D

= 10 V

V

GS

100

TJ = 25°C VGS = 0 V

t

f

t

d(off)

t

r

30

10

9

Q

T

8

7

6

5

Q

gs

Q

gd

4

3

2

, GATE−TO−SOURCE VOLTAGE (V)

1

GS

V

0

03146257108111391214

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−to−Source and Drain−to−Source

Voltage vs. Total Charge

30

VGS = 0 V

25

20

15

TJ = 125°C

ID = 30 A T

= 25°C

J

= 15 V

V

DD

V

= 10 A

GS

15 1716 18

TJ = 25°C

t, TIME (ns)

10

1

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

10

0 V < VGS < 10 V

1

0.1

Single Pulse TC = 25°C

RDS(on) LIMIT

, DRAIN CURRENT (A)

D

I

THERMAL LIMIT

0.01

PACKAGE LIMIT

0.10.01

1 10 100

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

t

d(on)

10 ms

100 ms

1 ms

10 ms

dc

10

, SOURCE CURRENT (A)

S

I

5

0

0.4 0.7 1.0

0.5 0.80.6 0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3

AVALANCHE ENERGY (mJ)

2 1

, SINGLE PULSE DRAIN−TO−SOURCE

0

AS

25 50 75 100 125 150 175

E

, STARTING JUNCTION TEMPERATURE (°C)

T

J

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

ID = 19 A

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5

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

DETAIL A

M

NTD4969N

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE B

C

A

c2

H

c

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.102

A1

H

0.118

3.00

C

Z

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.60

0.063

SCALE 3:1

6.17

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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6

SEATING PLANE

V

S

−T−

SEATING PLANE

F

V

W

F

B

R

4

123

G

B

R

G

A

K

3 PL

D

0.13 (0.005) T

NTD4969N

PACKAGE DIMENSIONS

3 IPAK, STRAIGHT LEAD

CASE 369AC−01

ISSUE O

C

E

A

K

J

H

D

3 PL

0.13 (0.005) W

IPAK

CASE 369D−01

ISSUE C

C

E

J

H

M

NOTES:

Z

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2.. CONTROLLING DIMENSION: INCH.

3. SEATING PLANE IS ON TOP OF DAMBAR POSITION.

4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.043 0.94 1.09 G 0.090 BSC 2.29 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27

W 0.000 0.010 0.000 0.25

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD4969N/D

7