Datasheet ntd4963n Datasheet

NTD4963N

Power MOSFET

30 V, 44 A, Single N−Channel, DPAK/IPAK

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• Three Package Variations for Design Flexibility

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

• CPU Power Delivery

• DC−DC Converters

• Recommended for High Side (Control)

to Minimize Conduction Losses

DS(on)

V

(BR)DSS

30 V

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R

MAX ID MAX

DS(ON)

9.6 mW @ 10 V

16 mW @ 4.5 V

D

44 A

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

Continuous Drain Current R (Note 2)

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Current Limited by Package TA = 25°C I

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 26 Apk, L = 0.1 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

(Note 1)

q

JA

(Note 2)

q

JA

(Note 1)

q

JC

q

JA

q

JA

q

JC

= 25°C unless otherwise stated)

J

TA = 25°C

TA = 85°C 7.2

TA = 25°C P

TA = 25°C

Steady

State

tp=10ms

TA = 85°C 5.8

TA = 25°C P

TC = 25°C

TC = 85°C 32

TC = 25°C P

TA = 25°C I

DSS

GS

I

D

ID

D

I

D

DM

DmaxPkg

TJ,

T

STG

S

EAS 33.8 mJ

T

L

30 V

±20 V

10.0

1.64 W

8.1

1.1 W

44

35.7 W

132 A

35 A

−55 to +175

30 A

260 °C

A

°C

G

S

N−CHANNEL MOSFET

2

3

IPAK

DPAK)

4

2

1

3

CASE 369AA

DPAK

(Bent Lead)

STYLE 2

4

CASE 369AC

(Straight Lead)

1

2

3 IPAK

4

3

1

CASE 369D

(Straight Lead

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Gate

Drain

1

49

YWW

2

Drain

63NG

3

Source

1

Gate

4

Drain

49

YWW

63NG

2

Drain

3

Source

Y = Year WW = Work Week 4963N = Device Code G = Pb−Free Package

Gate

Drain

1

4

49

YWW

2

Drain

63NG

3

Source

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

June, 2010 − Rev. 1

1 Publication Order Number:

NTD4963N/D

NTD4963N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−TAB (Drain)

Junction−to−Ambient – Steady State (Note 3)

Junction−to−Ambient – Steady State (Note 4)

3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

4. Surface−mounted on FR4 board using the minimum recommended pad size.

R

q

R

q

JC

JC−TAB

R

q

JA

R

q

JA

4.1

3.5

77

118

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage

V

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

T

J

DSS

GSS

/

VGS = 0 V, ID = 250 mA

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage V

Negative Threshold Temperature

V

Coefficient

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V

VGS = 4.5 V

Forward Transconductance g

FS

VDS = 1.5 V, ID = 30 A 40 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 12 V

VGS = 4.5 V, VDS = 15 V, ID = 30 A

VGS = 10 V, VDS = 15 V, ID = 30 A 16.2 nC

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

r

d(OFF)

f

VGS = 4.5 V, VDS = 15 V,

ID = 15 A, RG = 3.0 W

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

7. Assume terminal length of 110 mils.

30 V

25

TJ = 25°C 1.0

TJ = 125°C 10

1.45 2.5 V

5

ID = 30 A 8.2 9.6

ID = 15 A 8.2

ID = 30 A 13.6 16

ID = 15 A 13.6

1035

220

115

8.1

1.2

3.5

12

20

14

3

mV/°C

mA

mV/°C

mW

pF

nC

ns

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2

NTD4963N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter UnitMaxTypMinTest ConditionSymbol

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

r

d(OFF)

f

VGS = 11.5 V, VDS = 15 V,

ID = 15 A, RG = 3.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

SD

VGS = 0 V,

IS = 30 A

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

RR

a

b

RR

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 30 A

PACKAGE PARASITIC VALUES

Source Inductance (Note 7) L

Drain Inductance, DPAK L

Drain Inductance, IPAK (Note 7) L

Gate Inductance (Note 7) L

Gate Resistance R

S

D

G

TA = 25°C

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

7. Assume terminal length of 110 mils.

7.0

17

20

2

TJ = 25°C 0.96 1.2

TJ = 125°C 0.83

17

9

8

6 nC

2.49

0.0164

1.88

3.46

1.0

ns

V

ns

nH

W

ORDERING INFORMATION

Device Package Shipping

NTD4963NT4G DPAK

2500 / Tape & Reel

(Pb−Free)

NTD4963N−1G IPAK

75 Units / Rail

(Pb−Free)

NTD4963N−35G IPAK Trimmed Lead

75 Units / Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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3

NTD4963N

TYPICAL PERFORMANCE CURVES

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

021

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

2E−02

1.9E−02

1.8E−02

1.7E−02

1.6E−02

1.5E−02

1.4E−02

1.3E−02

1.2E−02

1.1E−02

1.0E−02 9E−03 8E−03 7E−03

, DRAIN−TO−SOURCE RESISTANCE (W)

6E−03 5E−03

DS(on)

R

4

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 3. On−Resistance vs. Gate−to−Source

4.6 V thru 10 V

TJ = 25°C

615

5793

Voltage

VGS = 4.4 V

4.2 V

4.0 V

3.8 V

3.6 V

3.4 V

3.2 V

2.8 V

3

41

ID = 30 A TJ = 25°C

8

5 1.5

10

60

VDS = 10 V

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

V

20E−03

15E−03

10E−03

5E−03

, DRAIN−TO−SOURCE RESISTANCE (W)

0E+00

DS(on)

R

TJ = 25°C

10

TJ = 25°C

TJ = 125°C

23

2.5 3.5 4.5

, GATE−TO−SOURCE VOLTAGE (V)

GS

20 4025

ID, DRAIN CURRENT (A)

TJ = −55°C

VGS = 4.5 V

VGS = 10 V

30

35 45

4 5.5

5

50

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

1.8

1.6

1.4

1.2

1.0

0.8

0.6

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

DS(on)

R

ID = 30 A V

= 10 V

GS

−50 250−25 50 75

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

125

100

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10,000

1,000

100

, LEAKAGE (nA)

DSS

I

150

4

VGS = 0 V

10

1

0.1 5

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

TJ = 150°C

TJ = 125°C

TJ = 25°C

1510 30

20

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

25

NTD4963N

TYPICAL PERFORMANCE CURVES

1200

C

iss

VGS = 0 V

1000

800

600

400

C

C, CAPACITANCE (pF)

oss

200

C

0

015

rss

5

10 25

20

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

1000

VDD = 15 V ID = 15 A VGS = 11.5 V

100

t, TIME (ns)

10

1

t

d(on)

t

f

1 10 100

RG, GATE RESISTANCE (W)

TJ = 25°C

t

d(off)

t

r

30

10

9

Q

T

8

7

6

Q

5

gs

Q

gd

4

3

2

, GATE−TO−SOURCE VOLTAGE (V)

1

GS

0

V

0

8

426 161412

10

ID = 30 A TJ = 25°C VDD = 15 V VGS = 30 A

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−to−Source and Drain−to−Source

Voltage vs. Total Charge

30

VGS = 0 V

25

TJ = 25°C

20

15

10

, SOURCE CURRENT (A)

S

I

5

0

0.5 0.6

0.4

0.7 0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (V)

0.8 1.0

18

1000

VGS = 30 V Single Pulse TC = 25°C

100

10

1

, DRAIN CURRENT (A)

D

I

0.1

0.01

0.1 1

Figure 11. Maximum Rated Forward Biased

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

10

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

dc

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

AS

100

E

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5

Figure 10. Diode Forward Voltage vs. Current

35

30

25

20

15

10

5

0

25

50 75

100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

ID = 26 A

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

150

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

DETAIL A

M

NTD4963N

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE B

C

A

c2

H

c

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.102

A1

H

3.00

0.118

C

Z

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61

c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC H 0.370 0.410 9.40 10.41 L 0.055 0.070 1.40 1.78

L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.60

0.063

SCALE 3:1

6.17

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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6

SEATING PLANE

l

V

S

−T−

SEATING PLANE

F

V

W

F

B

R

4

123

G

B

R

G

A

K

D 3 PL

0.13 (0.005) T

NTD4963N

PACKAGE DIMENSIONS

3 IPAK, STRAIGHT LEAD

CASE 369AC−01

ISSUE O

C

E

A

K

J

D

IPAK (STRAIGHT LEAD DPAK)

C

J

M

H

3 PL

0.13 (0.005) W

CASE 369D−01

ISSUE B

E

H

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2.. CONTROLLING DIMENSION: INCH.

3. SEATING PLANE IS ON TOP OF DAMBAR POSITION.

4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.043 0.94 1.09 G 0.090 BSC 2.29 BSC H 0.034 0.040 0.87 1.01

J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27 W 0.000 0.010 0.000 0.25

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

Z

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD4963N/D

7