Datasheet ntd4904n Datasheet

NTD4904N

Power MOSFET

30 V, 79 A, Single N−Channel, DPAK/IPAK

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These are Pb−Free Devices

Applications

• CPU Power Delivery

• DC−DC Converters

to Minimize Conduction Losses

DS(on)

(BR)DSS

30 V

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R

MAX

DS(on)

3.7 mW @ 10 V

5.5 mW @ 4.5 V

D

ID MAXV

79 A

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current (R (Note 1)

Power Dissipation (R

q

JA

Continuous Drain Current (R

2)

Power Dissipation (R

q

JA

Continuous Drain Current (R (Note 1)

Power Dissipation (R

q

JC

Pulsed Drain Current

Current Limited by Package TA = 25°C I

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, L = 0.1 mH, I

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

q

JA

) (Note 1)

q

JA

) (Note 2)

q

JC

) (Note 1)

)

) (Note

)

= 37 A, RG = 25 W)

L(pk)

= 25°C unless otherwise noted)

J

TA = 25°C

TA = 100°C 12.6

TA = 25°C P

TA = 25°C

Steady

State

tp=10ms

TA = 100°C 9.2

TA = 25°C P

TC = 25°C

TC = 100°C 56

TC = 25°C P

TA = 25°C I

DmaxPkg

E

DSS

GS

I

D

I

D

I

D

DM

S

AS

T

L

stg

30 V

"20 V

17.8

2.6 W

13

1.4 W

79

52 W

316 A

90 A

−55 to 175

47 A

68.4 mJ

260 °C

A

°C

4

3

N−Channel

4

1

2

3

CASE 369D

IPAK

(Straight Lead

DPAK)

G

2

1

3

CASE 369AA

DPAK

(Bent Lead)

STYLE 2

4

CASE 369AD

(Straight Lead)

1

IPAK

S

2

MARKING DIAGRAMS

Drain

YWW4904NG

Drain

1

Gate

& PIN ASSIGNMENTS

4

2

3

Source

Y = Year WW = Work Week 4904N = Device Code G = Pb−Free Package

Gate

1

4

Drain

YWW4904NG

2

Drain

3

Source

Gate

1

4

Drain

YWW4904NG

2

3

Drain

Source

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

June, 2010 − Rev. 1

1 Publication Order Number:

NTD4904N/D

NTD4904N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Tab (Drain)

Junction−to−Ambient − Steady State (Note 1)

Junction−to−Ambient − Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

R

q

R

q

JC

JC−TAB

R

q

JA

R

q

JA

2.9

4.3

57

108

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage

V

(BR)DSS

(BR)DSS/TJ

VGS = 0 V, ID = 250 mA

30 V

15 mV/°C

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

DSS

GSS

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = "20 V "100 nA

TJ = 25°C 1.0

TJ = 125°C 10

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature

V

GS(TH)

GS(TH)/TJ

VGS = VDS, ID = 250 mA

1.0 1.6 2.2 V

4.0 mV/°C

Coefficient

Drain−to−Source On Resistance R

DS(on)

VGS = 10 V

ID = 30 A 3.0 3.7

ID = 15 A 3.0

VGS = 4.5 V

ID = 30 A 4.0 5.5

ID = 15 A 4.0

Forward Transconductance gFS VDS = 1.5 V, ID = 30 A 76 S

CHARGES AND CAPACITANCES

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

iss

oss

rss

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS = 0 V, f = 1.0 MHz,

VDS = 15 V

VGS = 4.5 V, VDS = 15 V,

ID = 30 A

VGS = 10 V, VDS = 15 V,

3052

976

23

16.8

4.4

8.2

3.0

41 nC

ID = 30 A

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

r

d(off)

f

d(on)

r

d(off)

f

VGS = 4.5 V, VDS = 15 V,

ID = 15 A, R

= 3.0 W

G

VGS = 10 V, VDS = 15 V,

ID = 15 A, R

= 3.0 W

G

15.3

19.8

23.4

7.5

10.3

20

28.7

8.0

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

mA

mW

pF

nC

ns

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2

NTD4904N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Condition Min Typ Max Unit

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

SD

VGS = 0 V,

IS = 30 A

Reverse Recovery Time t

Charge Time ta 20.5

RR

VGS = 0 V, dIs/dt= 100 A/ms,

Discharge Time tb 19.9

Reverse Recovery Time Q

RR

TJ = 25°C 0.84 1.1

TJ = 125°C 0.7

IS = 30 A

PACKAGE PARASITIC VALUES

Source Inductance (Note 5) L

Drain Inductance, DPAK L

Drain Inductance, IPAK (Note 5) L

Gate Inductance (Note 5) L

Gate Resistance R

S

D

G

TA = 25°C

5. Assume terminal length of 110 mils.

40.4

35 nC

2.48

0.0164

1.88

4.9

1.0 2.0

V

ns

nH

W

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3

NTD4904N

TYPICAL PERFORMANCE CURVES

130

120

110

100

90 80 70 60 50 40 30

, DRAIN CURRENT (AMPS)

D

20

I

10

0

0521

V

DS

10 V

3.8 V to 6 V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.012

0.010

0.008

0.006

0.004

, DRAIN−TO−SOURCE RESISTANCE (W)

0.002

DS(on)

3

4

R

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

5

Figure 3. On−Resistance vs. Gate−to−Source

TJ = 25°C

3

610

789

3.6 V

3.4 V

3.2 V

3.0 V

2.8 V

2.6 V

2.4 V

4 2.52

ID = 30 A TJ = 25°C

130

VDS ≥ 10 V

120

110

100

90 80 70 60 50 40 30

, DRAIN CURRENT (AMPS)

D

20

I

10

0

0.006

0.005

0.004

0.003

, DRAIN−TO−SOURCE RESISTANCE (W)

0.002

DS(on)

20

R

TJ = 125°C

TJ = 25°C

, GATE−TO−SOURCE VOLTAGE (VOLTS)

V

GS

TJ = 25°C

40

ID, DRAIN CURRENT (AMPS)

TJ = −55°C

Figure 4. On−Resistance vs. Drain Current and

Voltage

3 3.5

VGS = 4.5 V

VGS = 10 V

60

80

Gate Voltage

100

4

120

2.2 ID = 30 A

2.0

1.8

1.6

1.4

1.2

(NORMALIZED)

1.0

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

−50 50250−25 75 125100

R

V

= 10 V

GS

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

10,000

1000

, LEAKAGE (nA)

100

DSS

I

10

175

150

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4

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 85°C

1510 305

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

20

25

Figure 6. Drain−to−Source Leakage Current

vs. Drain Voltage

NTD4904N

TYPICAL PERFORMANCE CURVES

3600

3200

2800

2400

2000

1600

1200

C, CAPACITANCE (pF)

800

400

0

1000

VDD = 15 V ID = 15 A VGS = 10 V

100

t, TIME (ns)

10

C

iss

C

oss

C

rss

5

TJ = 25°C VGS = 0 V

20

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

t

d(off)

t

f

t

r

t

d(on)

, GATE−TO−SOURCE VOLTAGE (VOLTS)

300101525

GS

V

12 11 10

Q

T

9

8

7

V

GS

6

Q

GS

GD

VDD = 15 V VGS = 10 V ID = 30 A TJ = 25°C

105

20 25

30 35 40

5

Q

4 3

2

1 0

0

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage vs. Total Charge

30

VGS = 0 V

25

20

15

10

TJ = 125°C

4515

1

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

10

VGS = 10 V SINGLE PULSE TC = 25°C

1

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1 1 100

R

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

10

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

dc

, SOURCE CURRENT (AMPS)

5

S

I

0

0.4

0.5

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

70

60

50

40

30

20

10

AVALANCHE ENERGY (mJ)

0

25

EAS, SINGLE PULSE DRAIN−TO−SOURCE

50 75 175

TJ, JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.6 0.7

100 125

TJ = 25°C

0.8 0.9

1.0

ID = 37 A

150

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5

100

10

1.0

R(t) (C/W)

0.1

0.01

0.001

50% (DUTY CYCLE)

20% 10%

5.0%

2.0%

1.0%

SINGLE PULSE

NTD4904N

TYPICAL PERFORMANCE CURVES

PSi TAB-A

0.0001 0.001 0.01 1.0

PULSE TIME (s)

Figure 13. FET Thermal Response

110

VDS = 1.5 V

100

90

80

70

60

50

GFS (S)

40

30

20

10

0

050

10

20 30 40 60 70

ID (A)

0.10.00001

80 90 100

10 1000.000001

1000

Figure 14. GFS vs ID

ORDERING INFORMATION

Order Number Package Shipping

NTD4904NT4G DPAK

(Pb−Free)

NTD4904N−1G IPAK

(Pb−Free)

NTD4904N−35G IPAK Trimmed Lead

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

2500 / Tape & Reel

75 Units / Rail

†

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6

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

DETAIL A

M

NTD4904N

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE B

C

A

c2

H

c

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.102

A1

H

3.00

0.118

C

Z

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.60

0.063

SCALE 3:1

6.17

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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7

−T−

l

SEATING PLANE

T

SEATING PLANE

NTD4904N

PACKAGE DIMENSIONS

IPAK (STRAIGHT LEAD DPAK)

CASE 369D−01

B

V

S

R

4

A

123

C

E

K

F

D

G

0.13 (0.005) T

J

H

3 PL

M

ISSUE B

Z

3.5 MM IPAK, STRAIGHT LEAD

CASE 369AD−01

ISSUE O

L2

L1

E

E3

D

L

b1

e

2X

b

3X

M

0.13 T

A1

A

A1

E2

D2

A2

E2

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88

E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01

J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45

S 0.025 0.040 0.63 1.01

V 0.035 0.050 0.89 1.27

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2.. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND

0.30mm FROM TERMINAL TIP.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH.

MILLIMETERS

DIM MIN MAX

A 2.19 2.38 A1 0.46 0.60 A2 0.87 1.10

b 0.69 0.89 b1 0.77 1.10

D 5.97 6.22 D2 4.80 −−−

E 6.35 6.73 E2 4.70 −−− E3 4.45 5.46

D2

e 2.28 BSC

L 3.40 3.60 L1 −−− 2.10 L2 0.89 1.27

MILLIMETERSINCHES

OPTIONAL

CONSTRUCTION

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD4904N/D

8