Datasheet ntd4860n Datasheet

NTD4860N

Power MOSFET

25 V, 65 A, Single N--Channel, DPAK/IPAK

Features

• Trench Technology

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These are Pb--Free Devices

Applications

• VCORE Applications

• DC--DC Converters

• High/Low Side Switching

to Minimize Conduction Losses

DS(on)

V

(BR)DSS

25 V

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R

7.5 mΩ @10V

11. 1 mΩ @4.5V

MAX IDMAX

DS(ON)

D

65 A

MAXIMUM RATINGS (T

Parameter

Drain--to--Source Voltage V

Gate--to--Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

Continuous Drain Current R (Note 2)

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Current Limited by Package TA=25°C I

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6 V/ns

Single Pulse Drain --to-- Source Avalanche Energy (T I

L

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

θ

JA

(Note 1)

θ

JA

θ

JA

(Note 2)

θ

JA

θ

JC

(Note 1)

θ

JC

=25°C, VDD=50V,VGS=10V,

J

=13Apk,L=1.0mH,RG=25Ω)

=25°C unless otherwise stated)

J

TA=25°C

TA=85°C 10

TA=25°C P

TA=25°C

Steady

State

tp=10ms

TA=85°C 8.0

TA=25°C P

TC=25°C

TC=85°C 50

TC=25°C P

TA=25°C I

Symbol Value Unit

DSS

GS

I

D

ID

D

I

D

DM

DmaxPkg

TJ,

T

STG

S

EAS 84.5 mJ

T

L

25 V

±20 V

13

2.0 W

10.4

1.28 W

65

50 W

130 A

45 A

-- 5 5 t o +175

42 A

260 °C

A

°C

2

1

3

CASE 369AA

DPAK

(Bent Lead)

STYLE 2

4

Drain

48

YWW

60NG

2

Drain

1

Gate

Source

G

S

N--CHANNEL MOSFET

4

1

2

3

CASE 369AC

3IPAK

(Straight Lead)

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

48

YWW

60NG

2

1

3

Gate

Y = Year WW = Work Week 4860N = Device Code G = Pb--Free Package

Drain

3

Source

Gate

4

1

2

3

CASE 369D

IPAK

(Straight Lead

DPAK)

4

Drain

48

YWW

60NG

2

1

3

Drain

Source

June, 2010 -- Rev. 1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

1 Publication Order Number:

NTD4860N/D

NTD4860N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction--to--Case (Drain)

Junction--to--TAB (Drain)

Junction--to--Ambient – Steady State (Note 1)

Junction--to--Ambient – Steady State (Note 2)

1. Surface--mounted on FR4 board using 1 sq--in pad, 1 oz Cu.

2. Surface--mounted on FR4 board using the minimum recommended pad size.

R

θ

R

θ

JC

JC--TAB

R

θ

JA

R

θ

JA

3.5

75

117

3

°C/W

ELECTRICAL CHARACTERISTICS (T

=25°C unless otherwise specified)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain--to--Source Breakdown Voltage

Drain--to--Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate--to--Source Leakage Current I

V

(BR)DSS

V

(BR)DSS

T

DSS

GSS

VGS=0V,ID= 250 mA

/

J

VGS=0V,

=20V

V

DS

VDS=0V,VGS= ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain--to--Source On Resistance R

V

GS(TH)

V

GS(TH)/TJ

DS(on)

VGS=VDS,ID= 250 mA

VGS=10V ID=30A 6.1 7.5

VGS=4.5V ID=30A 8.9 11.1

Forward Transconductance g

FS

VDS=1.5V,ID=15A 48 S

CHARGES AND CAPACITANCES

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate--to--Source Charge Q

Gate--to--Drain Charge Q

Total Gate Charge Q

C

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS=0V,f=1.0MHz,VDS=12V

VGS=4.5V,VDS=15V,ID=30A

VGS=10V,VDS=15V,ID=30A 21.8 nC

SWITCHING CHARACTERISTICS (Note 4)

Turn--On Delay Time

Rise Time t

Turn--Off Delay Time t

Fall Time t

Turn--On Delay Time t

Rise Time t

Turn--Off Delay Time t

Fall Time t

t

d(ON)

r

d(OFF)

f

d(ON)

r

d(OFF)

f

VGS=4.5V,VDS=15V,

I

=15A,RG=3.0Ω

D

VGS=11.5V,VDS=15V,

I

=15A,RG=3.0Ω

D

3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

25 V

21

TJ=25°C 1.0

TJ= 125°C 10

1.45 2.5 V

5.2

1308

342

169

11 16.5

1.2

3.9

4.7

12.2

20.1

15.2

4.3

7.1

17

22

2.3

mV/°C

mA

mV/°C

mΩ

pF

nC

ns

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2

NTD4860N

ELECTRICAL CHARACTERISTICS (T

=25°C unless otherwise specified)

J

Parameter UnitMaxTypMinTest ConditionSymbol

DRAIN--SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

V

SD

RR

a

b

RR

VGS=0V,

=30A

I

S

VGS= 0 V, dIS/dt = 100 A/ms,

=30A

I

S

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance, DPAK L

Drain Inductance, IPAK L

Gate Inductance L

Gate Resistance R

L

S

D

G

TA=25°C

3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

TJ=25°C 0.9 1.2

TJ= 125°C 0.76

12.7

7.0

5.7

3.5 nC

2.49

0.0164

1.88

3.46

0.75

V

ns

nH

Ω

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3

NTD4860N

TYPICAL PERFORMANCE CURVES

60

10V

50

40

30

20

, DRAIN CURRENT (AMPS)

10

D

I

0

012345

V

DS

4V

TJ=25°C

, DRAIN--TO--SOURCE VOLTAGE (VOLTS)

3.8 V

3.6 V

3.4 V

3.2 V

3.0 V

2.8 V

Figure 1. On--Region Characteristics Figure 2. Transfer Characteristics

0.040

0.036

0.032

0.028

0.024

0.020

0.016

0.012

0.008

, DRAIN--TO--SOURCE RESISTANCE (Ω)

0.004

0

DS(on)

246810

R

357911

VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)

ID=30A T

=25°C

J

Figure 3. On--Resistance vs. Gate--to --Source

Volta g e

60

VDS≥ 10 V

50

40

30

20

, DRAIN CURRENT (AMPS)

10

D

I

0

02345

0.012

0.011

0.010

0.009

0.008

0.007

0.006

0.005

, DRAIN--TO--SOURCE RESISTANCE (Ω)

0.004

DS(on)

R

1

VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)

TJ=25°C

20 40 6010 30 50

TJ= 125°C

TJ=25°C

TJ=--55°C

VGS=4.5V

VGS=11.5V

ID, DRAIN CURRENT (AMPS)

Figure 4. On--Resistance vs. Drain Current and

Gate Voltage

1.8

ID=30A

1.6

V

=10V

GS

1.4

1.2

1.0

(NORMALIZED)

0.8

, DRAIN--TO--SOURCE RESISTANCE

0.6

--25 25 75 125 175

--50 0 50 100 150

DS(on)

R

TJ, J UNCTION TEMPERATURE (°C)

Figure 5. On-- Resistance Variation with

Temperature

10000

1000

, LEAKAGE (nA)

100

DSS

I

10

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4

VGS=0V

TJ= 150°C

TJ= 125°C

214161820

4681012

VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)

Figure 6. Drain--to--Source Leakage Current

vs. Drain Voltage

NTD4860N

2000

10

TYPICAL PERFORMANCE CURVES

C

1500

iss

1000

C

oss

500

C, CAPACITANCE (pF)

C

rss

0

01015

5

20

DRAIN--TO--SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

VDD=15V I

=15A

D

V

=11.5V

GS

100

t

d(off)

t

t, TIME (ns)

10

1

1 10 100

r

t

d(on)

t

f

RG, G ATE RESISTANCE (OHMS)

VGS=0V

TJ=25°C

25

Q

T

8

6

Q

4

Q

1

2

V

GS

2

ID=30A T

=25°C

0

, GATE--TO--SOURCE VOLTAGE (VOLTS)

015

V

GS

QG, TOTAL GATE CHARGE (nC)

10 20525

J

Figure 8. Gate--To--Source and Drain--To--Source

Voltage vs. Total Charge

30

VGS=0V

TJ=25°C

25

20

15

10

5

, SOURCE CURRENT (AMPS)

S

I

0

0.4 0.7

0.5 0.9

0.6 0.8

VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS)

1.0

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

10 ms

10

VGS=20V

100 ms

1ms

SINGLE PULSE

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1 10 100

R

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

1 25 125 175

T

=25°C

C

1

VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

100

10 ms dc

AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAIN--TO-- SOURCE

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Figure 10. Diode Forward Voltage vs. Current

90

80

70

60

50

40

30

20

10

0

75

T

, J UNCTION TEMPERATURE (°C)

J

100 15050

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

ID=13A

NTD4860N

TYPICAL PERFORMANCE CURVES

1.0

D=0.5

0.2

0.1

0.05

0.1

0.02

(NORMALIZED)

0.01

SINGLE PULSE

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

Figure 13. Thermal Response

ORDERING INFORMATION

Device Package Shipping

NTD4860NT4G DPAK

NTD4860N--1G IPAK

NTD4860N--35G IPAK Trimmed Lead

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

P

(pk)

t

1

DUTY CYCLE, D = t1/t

t, TIME (ms)

(Pb--Free)

(3.5  0.15 mm)

(Pb--Free)

R

(t) = r(t) R

θ

JC

θ

JC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN

2

T

-- TC=P

J(pk)

2

t

READ TIME AT t

(pk)

1

R

(t)

θ

JC

1.0E+00 1.0E+011.0E--011.0E--021.0E--031.0E--041.0E--05

†

2500 / Tape & Reel

75 Units / Rail

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6

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

DETAIL A

M

NTD4860N

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA--01

ISSUE B

C

A

c2

H

c

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW°

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.102

A1

H

0.118

3.00

C

Z

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 -- -- -- 0 . 0 4 0 -- -- -- 1 . 0 1

Z 0.155 ------ 3.93 ------

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.60

0.063

SCALE 3:1

6.17

0.243



inches

mm



*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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7

SEATING PLANE

l

NTD4860N

PACKAGE DIMENSIONS

3 IPAK, STRAIGHT LEAD

CASE 369AC--01

ISSUE O

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

B

V

R

C

E

A

W

F

G

K

J

H

D

3PL

0.13 (0.005) W

IPAK (STRAIGHT LEAD DPAK)

CASE 369D--01

ISSUE B

2.. CONTROLLING DIMENSION: INCH.

3. SEATING PLANE IS ON TOP OF DAMBAR POSITION.

4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.043 0.94 1.09 G 0.090 BSC 2.29 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27 W 0.000 0.010 0.000 0.25

MILLIMETERSINCHES

B

V

S

R

4

A

123

-- T --

SEATING PLANE

K

F

3PL

D

G

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to any products herein. SCILLC makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights o f others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

0.13 (0.005) T

C

E

J

H

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

Z

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 ------ 3.93 ------

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

PUBLICATION ORDERING INFORMATION

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NTD4860N/D

8