Page 1
NTD4808N
Power MOSFET
30 V, 63 A, Single N--Channel, DPAK/IPAK
Features
• Low R
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• These are Pb--Free Devices
Applications
• CPU Power Delivery
• DC--DC Converters
• Low Side Switching
to Minimize Conduction Losses
DS(on)
V
(BR)DSS
30 V
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R
8.0 mΩ @10V
12.4 m Ω @4.5V
MAX IDMAX
DS(ON)
D
63 A
MAXIMUM RATINGS (T
Parameter
Drain--to--Source Voltage V
Gate--to--Source Voltage V
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Continuous Drain
Current R
(Note 2)
Power Dissipation
R
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Pulsed Drain
Current
Current Limited by Package TA=25°C I
Operating Junction and Storage
Temperature
Source Current (Body Diode) I
Drain to Source dV/dt dV/dt 6 V/ns
Single Pulse Drain --to-- Source Avalanche
Energy (V
I
L
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
θ
JA
(Note 1)
θ
JA
θ
JA
(Note 2)
θ
JA
θ
JC
(Note 1)
θ
JC
=24V,VGS=10V,
DD
=17Apk,L=1.0mH,RG=25Ω)
=25°C unless otherwise stated)
J
TA=25°C
TA=85°C 9.5
TA=25°C P
TA=25°C
Steady
State
tp=10ms
TA=85°C 7.5
TA=25°C P
TC=25°C
TC=85°C 49
TC=25°C P
TA=25°C I
Symbol Value Unit
DSS
GS
I
D
D
ID
D
I
D
D
DM
DmaxPkg
TJ,
T
STG
S
EAS 144.5 mJ
T
L
30 V
±20 V
12
2.0 W
9.8
1.3 W
63
54.6 W
126 A
45 A
-- 5 5 t o
+175
45 A
260 °C
A
A
A
°C
2
1
3
DPAK
CASE 369AA
STYLE 2
4
Drain
YWW4808NG
2
Drain
1
Gate
3
Source
G
S
N--CHANNEL MOSFET
4
4
1
2
3
3IPAK
(STRAIGHT LEAD)
CASE 369AC
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
YWW4808NG
2
1
3
Drain
Gate
Y = Year
WW = Work Week
4808N = Device Code
G = Pb--Free Package
Source
Gate
1
2
3
IPAK
CASE 369D
STYLE 2
4
Drain
YWW4808NG
2
1
3
Drain
Source
4
© Semiconductor Components Industries, LLC, 2010
June, 2010 -- Rev. 5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1 Publication Order Number:
NTD4808N/D
Page 2
NTD4808N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction--to--Case (Drain)
Junction--to--TAB (Drain)
Junction--to--Ambient – S teady State (Note 1)
Junction--to--Ambient – S teady State (Note 2)
1. Surface--mounted on FR4 board using 1 sq--in pad, 1 oz Cu.
2. Surface--mounted on FR4 board using the minimum recommended pad size.
R
θ
R
θ
JC
JC--TAB
R
θ
JA
R
θ
JA
2.75
3.5
73.5
116
°C/W
ELECTRICAL CHARACTERISTICS (T
=25°C unless otherwise specified)
J
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain--to--Source Breakdown Voltage
Drain--to--Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate--to--Source Leakage Current I
V
(BR)DSS
V
(BR)DSS
T
DSS
GSS
VGS=0V,ID= 250 mA
/
J
VGS=0V,
=24V
V
DS
VDS=0V,VGS= ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
Drain--to--Source On Resistance R
V
GS(TH)
V
GS(TH)/TJ
DS(on)
VGS=VDS,ID= 250 mA
VGS=10to11.5V
VGS=4.5V
Forward Transconductance g
FS
VDS=15V,ID=15A 11. 4 S
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate--to--Source Charge Q
Gate--to--Drain Charge Q
Total Gate Charge Q
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
G(TOT)
VGS=0V,f=1MHz,VDS=12V
VGS=4.5V,VDS=15V;ID=30A
VGS=11.5V,VDS=15V;
=30A
I
D
SWITCHING CHARACTERISTICS (Note 4)
Turn--On Delay Time
Rise Time t
Turn--Off Delay Time t
Fall Time t
t
d(ON)
r
d(OFF)
f
VGS=4.5V,VDS=15V,ID=15A,
R
=3.0Ω
G
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
30 V
27
TJ=25°C 1
TJ= 125°C 10
1.5 2.5 V
5.6
ID=30A 6.7 8.0
ID=15A 6.6
ID=30A 10.3 12.4
ID=15A 9.8
1538
334
180
11. 3 13
1.6
4.9
4.9
26 nC
12.3
21.3
14.6
6.0
mV/°C
mA
mV/°C
mΩ
pF
nC
ns
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2
Page 3
NTD4808N
ELECTRICAL CHARACTERISTICS (T
=25°C unless otherwise specified)
J
Parameter UnitMaxTypMinTest ConditionSymbol
SWITCHING CHARACTERISTICS (Note 4)
Turn--On Delay Time
Rise Time t
Turn--Off Delay Time t
Fall Time t
t
d(ON)
r
d(OFF)
f
VGS=11.5V,VDS=15V,
I
=15A,RG=3.0Ω
D
DRAIN--SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS=0V,
=30A
I
S
VGS=0V,dIS/dt = 100 A/ms,
=30A
I
S
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance, DPAK L
Drain Inductance, IPAK L
Gate Inductance L
Gate Resistance R
L
S
D
D
G
G
TA=25°C
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
7.7
19.5
23
3.5
TJ=25°C 0.93 1.2
TJ= 125°C 0.83
20
10.4
9.6
9.7 nC
2.49
0.0164
1.88
3.46
1.1
ns
V
ns
nH
Ω
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3
Page 4
NTD4808N
TYPICAL PERFORMANCE CURVES
100
90
80
70
60
50
40
30
, DRAIN CURRENT (AMPS)
20
D
I
10
0
05
V
DS
5.5 V to 10 V
21
, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
4.5 V
3
TJ=25°C
4
4V
3.8 V
3.6 V
3.4 V
3.2 V
3V
80
70
60
50
40
30
20
, DRAIN CURRENT (AMPS)
D
I
10
0
1
VDS≥ 10 V
TJ= 125°C
TJ=25°C
23
, GATE--TO--SOURCE VOLTAGE (VOLTS)
V
GS
Figure 1. On--Region Characteristics Figure 2. Transfer Characteristics
, DRAIN--TO--SOURCE RESISTANCE (mΩ)
R
DS(on)
10
9.6
9.2
8.8
8.4
8.0
7.6
7.2
6.8
6.4
6.0
5
610
5.5
6.5
789
7.5 8.5 9.5 10.5 11 11.5
VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)
Figure 3. On-- Resistance vs. Gate--to --Source
Volta g e
ID=30A
T
=25°C
J
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
, DRAIN--TO--SOURCE RESISTANCE (Ω)
0.002
DS(on)
R
TJ=25°C
VGS=4.5V
VGS=11.5V
0
10
2015
30
25 35
ID, DRAIN CURRENT (AMPS)
Figure 4. On--Resistance vs. Drain Current and
Gate Voltage
TJ=--55°C
40
45
45
50
55
60
1.8
1.7
ID=30A
V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
(NORMALIZED)
0.9
0.8
, DRAIN--TO--SOURCE RESISTANCE
0.7
0.6
DS(on)
--50 50250--25 75 125100
R
=10V
GS
TJ, J UNCTION TEMPERATURE (°C)
Figure 5. On--Resistance Variation with
Temperature
10000
1000
100
10
, LEAKAGE (nA)
DSS
I
1
150
175
0.1
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4
VGS=0V
TJ= 150°C
TJ= 125°C
TJ=25°C
1510 305
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
20
25
Figure 6. Drain-- to--Source Leakage Current
vs. Drain Voltage
Page 5
NTD4808N
TYPICAL PERFORMANCE CURVES
2000
TJ=25°C
C
1500
iss
1000
500
C, CAPACITANCE (pF)
0
0101525
5
C
oss
C
rss
20
GATE--TO- -SOURCE OR DRAIN--TO-- SOURCE VOLTAGE (VOL TS)
Figure 7. Capacitance Variation
100
t
r
t
d(off)
10
t
t, TIME (ns)
1
d(on)
t
f
VDD=15V
I
=30A
D
V
=11.5V
GS
, SOURCE CURRENT (AMPS)
1 10 100
RG, G ATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
5
Q
T
Q
4
1
Q
2
3
2
VDD=15V
, GATE--TO--SOURCE VOLTAGE (VOLTS)
GS
V
1
0
0
23456789
, TOTAL GATE CHARGE (nC)
Q
G
V
I
D
T
Figure 8. Gate--To--Source and Drain--To-- Source
Voltage vs. Total Charge
30
VGS=0V
TJ=25°C
25
20
15
10
5
S
I
0
0.5
0.6 0.7 1.0
, SOURCE--TO--DRAIN VOLTAGE (VOLTS)
V
SD
0.8 0.9
Figure 10. Diode Forward Voltage vs. Current
=4.5V
GS
=30A
=25°C
J
101
1211
1000
VGS=20V
SINGLE PULSE
T
=25°C
C
100
10
, DRAIN CURRENT (AMPS)
D
I
1
0.1 1 100
V
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
100
10 ms
100 ms
1ms
10 ms
dc
AVALANCHE ENERGY (mJ)
EAS, SINGLE PULSE DRAIN--TO-- SOURCE
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5
90
ID=17A
80
70
60
50
40
30
20
10
0
50 75 175
T
J
100 125
150
, J UNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
Page 6
100
NTD4808N
TYPICAL PERFORMANCE CURVES
25°C
100°C
(NORMALIZED)
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
1.0
0.1
D=0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
10
, DRAIN CURRENT (AMPS)
D
I
1
125°C
10
PULSE WIDTH (ms)
Figure 13. Avalanche Characteristics
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
t, TIME (ms)
Figure 14. Thermal Response
10001 100
R
(t) = r(t) R
θ
JC
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
-- TC=P
J(pk)
2
(pk)
1
R
(t)
θ
JC
1.0E+00 1.0E+011.0E--011.0E--021.0E--031.0E--041.0E--05
ORDERING INFORMATION
Device Package Shipping
NTD4808NT4G DPAK
2500 / Tape & Reel
(Pb--Free)
NTD4808N--1G IPAK
75 Units / Rail
(Pb--Free)
NTD4808N--35G IPAK Trimmed Lead
75 Units / Rail
(3.5 ± 0.15 mm)
(Pb--Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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6
Page 7
L3
L4
b2
e
E
b3
4
12 3
A
B
D
b
0.005 (0.13) C
DETAIL A
M
NTD4808N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA--01
ISSUE B
C
A
c2
H
c
GAUGE
L2
PLANE
L
L1
DETAIL A
ROTATED 90 CW°
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
A1
H
0.118
3.00
C
Z
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN
DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
DIM MIN MAX MIN MAX
A 0.086 0.094 2.18 2.38
A1 0.000 0.005 0.00 0.13
b 0.025 0.035 0.63 0.89
b2 0.030 0.045 0.76 1.14
b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
L3 0.035 0.050 0.89 1.27
L4 -- -- -- 0 . 0 4 0 -- -- -- 1 . 0 1
Z 0.155 ------ 3.93 ------
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
5.80
0.228
1.60
0.063
SCALE 3:1
6.17
0.243
inches
mm
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
Page 8
SEATING PLANE
NTD4808N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC--01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
B
V
R
C
E
A
W
F
G
K
J
H
D
3PL
0.13 (0.005) W
IPAK (STRAIGHT LEAD DPAK)
CASE 369D--01
ISSUE B
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.043 0.94 1.09
G 0.090 BSC 2.29 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.134 0.142 3.40 3.60
R 0.180 0.215 4.57 5.46
V 0.035 0.050 0.89 1.27
W 0.000 0.010 0.000 0.25
MILLIMETERSINCHES
B
V
S
R
4
A
123
-- T --
SEATING
PLANE
K
F
3PL
D
G
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights o f others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
0.13 (0.005) T
C
E
J
H
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
0.090 BSC 2.29 BSC
G
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 ------ 3.93 ------
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution C enter for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada
Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81--3--5773-- 3850
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8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD4808N/D
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