Datasheet ntd4806n Datasheet

NTD4806N

Power MOSFET

30 V, 76 A, Single N−Channel, DPAK/IPAK

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These are Pb−Free Devices

Applications

• CPU Power Delivery

• DC−DC Converters

• Low Side Switching

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current (R

Power Dissipation

) (Note 1)

(R

q

JA

Continuous Drain Current (R

Power Dissipation

) (Note 2)

(R

q

JA

Continuous Drain Current (R (Note 1)

Power Dissipation

) (Note 1)

(R

q

JC

Pulsed Drain Current

Current Limited by Package TA = 25°C I

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy (V L = 1.0 mH, I

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise noted)

J

Parameter

) (Note 1)

q

JA

) (Note 2)

q

JA

)

q

JC

= 24 V, VGS = 10 V,

DD

= 21 A, RG = 25 W)

L(pk)

Steady

State

tp=10ms

TA = 25°C

TA = 85°C 11

TA = 25°C P

TA = 25°C

TA = 85°C 8.8

TA = 25°C P

TC = 25°C

TC = 85°C 59

TC = 25°C P

TA = 25°C I

Symbol Value Unit

DSS

GS

I

D

I

D

I

D

DM

DmaxPkg

stg

S

E

AS

T

L

30 V

"20 V

14

2.14 W

11

1.33 W

76

60 W

150 A

45 A

−55 to 175

50 A

220 mJ

260 °C

A

°C

(BR)DSS

30 V

2

1

3

CASE 369AA

DPAK

(Bent Lead)

STYLE 2

4

Drain

YWW4806NG

2

Drain

1

Gate

Source

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R

MAX

DS(on)

6.0 mW @ 10 V

9.4 mW @ 4.5 V

D

G

S

4

1

2

3

CASE 369AD

IPAK

(Straight Lead)

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

YWW4806NG

2

1

3

Gate

Y = Year WW = Work Week 4806N = Device Code G = Pb−Free Package

Drain

3

Source

Gate

ID MAXV

76 A

N−Channel

4

1

2

3

CASE 369D

IPAK

(Straight Lead

DPAK)

4

Drain

YWW4806NG

2

1

3

Drain

Source

April, 2011 − Rev. 7

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

1 Publication Order Number:

NTD4806N/D

NTD4806N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Tab (Drain)

Junction−to−Ambient − Steady State (Note 1)

Junction−to−Ambient − Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

R

q

R

q

JC

JC−TAB

R

q

JA

R

q

JA

2.5

3.5

70

113

°C/W

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise noted)

J

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

V

(BR)DSS

V

(BR)DSS/TJ

VGS = 0 V, ID = 250 mA

30 V

27 mV/°C

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

DSS

GSS

VGS = 0 V,

= 24 V

V

DS

VDS = 0 V, VGS = "20 V "100 nA

TJ = 25°C 1.0

TJ = 125°C 10

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature

V

GS(TH)

V

GS(TH)/TJ

VGS = VDS, ID = 250 mA

1.5 2.5 V

6.0 mV/°C

Coefficient

Drain−to−Source On Resistance R

DS(on)

VGS = 10 to 11.5 V

ID = 30 A 4.9 6.0

ID = 15 A 4.8

VGS = 4.5 V

ID = 30 A 7.9 9.4

ID = 15 A 7.5

Forward Transconductance gFS VDS = 15 V, ID = 15 A 14 S

CHARGES AND CAPACITANCES

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

C

iss

oss

rss

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS = 0 V, f = 1.0 MHz,

= 12 V

V

DS

VGS = 4.5 V, VDS = 15 V,

= 30 A

I

D

VGS = 11.5 V, VDS = 15 V,

= 30 A

I

D

2142

480

251

15 23

3.0

7.0

37 nC

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

t

d(on)

d(off)

d(on)

d(off)

13.9

r

f

VGS = 4.5 V, VDS = 15 V,

I

= 15 A, R

D

= 3.0 W

G

29.7

18.3

7.8

8.5

r

f

VGS = 11.5 V, VDS = 15 V,

I

= 15 A, R

D

= 3.0 W

G

23.8

26

4.7

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

mA

mW

pF

nC

ns

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2

NTD4806N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Parameter Symbol Test Condition Min Typ Max Unit

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time ta 13

Discharge Time tb 13

Reverse Recovery Time Q

V

SD

RR

VGS = 0 V,

= 30 A

I

S

TJ = 25°C 0.9 1.2

TJ = 125°C 0.8

VGS = 0 V, dIs/dt= 100 A/ms,

= 30 A

I

S

RR

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance, DPAK L

Drain Inductance, IPAK L

Gate Inductance L

Gate Resistance R

L

S

D

G

TA = 25°C

26

16 nC

2.49

0.0164

1.88

3.46

1.0

V

ns

nH

W

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3

NTD4806N

TYPICAL PERFORMANCE CURVES

100

90

80

70

60

6 V

5 V

4.5 V

10 V

4.2 V

4 V

50

40

30

, DRAIN CURRENT (AMPS)

20

D

I

10

3.8 V

3.6 V

3.4 V

3.2 V

0

05

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

21

3

4

160

VDS ≥ 10 V

150 140 130 120 110 100

90

80 70 60 50

40

, DRAIN CURRENT (AMPS)

30

D

I

20 10

0

10

V

GS

TJ = 25°C

23

, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = 125°C

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.048

0.043

0.038

0.033

0.028

0.023

0.018

0.013

, DRAIN−TO−SOURCE RESISTANCE (W)

0.008

0.003

DS(on)

R

ID = 30 A T

= 25°C

J

3

4

5

789

610

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

0.015

0.010

0.005

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

R

TJ = 25°C

VGS = 4.5 V

VGS = 11.5 V

0

55 65 75 85

50

60

70

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

TJ = −55°C

45

80

6

90

2.0

ID = 30 A V

= 10 V

GS

1.5

1.0

(NORMALIZED)

0.5

, DRAIN−TO−SOURCE RESISTANCE

0

DS(on)

−50 50250−25 75 125100

R

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

100,000

10,000

1000

, LEAKAGE (nA)

DSS

I

100

10

175

150

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4

VGS = 0 V

TJ = 175°C

TJ = 125°C

1510 255

20

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Drain Voltage

NTD4806N

TYPICAL PERFORMANCE CURVES

4000

3000

C

iss

VGS = 0 VVDS = 0 V

TJ = 25°C

C

iss

2000

C

rss

1000

C, CAPACITANCE (pF)

C

oss

C

0

10 0 10 15 25

55

rss

20

V

GS

V

DS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

VDD = 15 V I

= 30 A

D

= 11.5 V

V

GS

100

t

r

8

6

Q

4

1

T

Q

2

ID = 30 A V

= 4.5 V

GS

= 25°C

T

J

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

V

0

, TOTAL GATE CHARGE (nC)

Q

G

105

Figure 8. Gate−To−Source and Drain−To−Source

Voltage vs. Total Charge

30

VGS = 0 V

TJ = 25°C

25

20

V

GS

2015

t

d(off)

t, TIME (ns)

10

t

d(on)

t

f

1

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

10

VGS = 20 V SINGLE PULSE TC = 25°C

1

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1 1 100 V

R

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

10

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms dc

15

10

, SOURCE CURRENT (AMPS)

5

S

I

0

0.5

0.6 0.7 1.0

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

V

SD

Figure 10. Diode Forward Voltage vs. Current

250

200

150

100

50

AVALANCHE ENERGY (mJ)

0

25

EAS, SINGLE PULSE DRAIN−TO−SOURCE

50 75 175

T

, JUNCTION TEMPERATURE (°C)

J

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.8 0.9

100 125

ID = 21 A

150

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5

100

NTD4806N

TYPICAL PERFORMANCE CURVES

1.0

D = 0.5

0.05

0.1

0.02

(NORMALIZED)

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

0.2

0.1

0.01

SINGLE PULSE

10

, DRAIN CURRENT (AMPS)

D

I

1

25°C

125°C

100°C

10

PULSE WIDTH (ms)

Figure 13. Avalanche Characteristics

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

t, TIME (ms)

Figure 14. Thermal Response

10001 100

R

(t) = r(t) R

q

JC

q

JC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

− TC = P

J(pk)

2

(pk)

1

R

(t)

q

JC

1.0E+00 1.0E+011.0E-011.0E-021.0E-031.0E-041.0E-05

ORDERING INFORMATION

Order Number Package Shipping

NTD4806NT4G DPAK

(Pb−Free)

NTD4806N−1G IPAK

(Pb−Free)

2500 Tape & Reel

75 Units/Rail

NTD4806N−35G IPAK Trimmed Lead

(3.5 " 0.15 mm)

75 Units/Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

http://onsemi.com

6

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

DETAIL A

M

NTD4806N

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE B

C

A

c2

H

c

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

0.102

2.58

A1

H

0.118

3.00

Z

SEATING

C

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.60

0.063

SCALE 3:1

6.17

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

7

−T−

SEATING PLANE

T

SEATING PLANE

NTD4806N

PACKAGE DIMENSIONS

IPAK (STRAIGHT LEAD DPAK)

CASE 369D−01

B

V

S

R

4

A

123

C

E

K

F

D

G

0.13 (0.005) T

J

H

3 PL

M

ISSUE B

Z

3.5 MM IPAK, STRAIGHT LEAD

CASE 369AD−01

ISSUE O

L2

L1

E

E3

D

L

b1

e

2X

b

3X

M

0.13 T

A1

A

A1

E2

D2

A2

E2

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G

H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2.. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND

0.30mm FROM TERMINAL TIP.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH.

MILLIMETERS

DIM MIN MAX

A 2.19 2.38 A1 0.46 0.60 A2 0.87 1.10

b 0.69 0.89

b1 0.77 1.10

D 5.97 6.22 D2 4.80 −−−

E 6.35 6.73 E2 4.70 −−− E3 4.45 5.46

D2

e 2.28 BSC

L 3.40 3.60 L1 −−− 2.10 L2 0.89 1.27

MILLIMETERSINCHES

OPTIONAL

CONSTRUCTION

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD4806N/D

8