Datasheet ntd3055l104 Datasheet

Page 1

NTD3055L104

Power MOSFET

12 Amps, 60 Volts, Logic Level N−Channel DPAK

Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.

Features

• Lower R

• Lower V

• Tighter V

• Lower Diode Reverse Recovery Time

• Lower Reverse Recovery Stored Charge

• These Devices are Pb−Free and are RoHS Compliant

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

DS(on)

Specification

(BR)DSS

60 V

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TYP

DS(on)

104 mW

N−Channel

ID MAXV

12 A

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Drain−to−Gate Voltage (RGS = 10 MW)

Gate−to−Source Voltage, Continuous

− Non−Repetitive (tpv10 ms)

Drain Current

− Continuous @ TA = 25°C

− Continuous @ TA = 100°C

− Single Pulse (tpv10 ms)

Total Power Dissipation @ TA = 25°C

Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2)

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH

= 11 A, VDS = 60 Vdc)

L(pk)

Thermal Resistance, − Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).

2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).

= 25°C unless otherwise noted)

Rating Symbol Value Unit

stg

60 Vdc

"15 "20

12 10 45

0.32

2.1

1.5

−55 to +175

61 mJ

3.13

71.4

100

260 °C

Vdc

Adc

Apk

W/°C

W W

°C

°C/W

V V

R R R

DSS

DGR

I I

MARKING

DIAGRAMS

Drain

DPAK

CASE 369C

STYLE 2

DPAK−3

CASE 369D

STYLE 2

55L104 = Device Code Y = Year WW = Work Week G = Pb−Free Package

Gate

YWW

Drain

YWw

Drain

55L

104G

3 Source

104G

3 Source

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

October, 2010 − Rev. 7

1 Publication Order Number:

NTD3055L104/D

Page 2

NTD3055L104

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

= 0 Vdc, ID = 250 mAdc)

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(VDS = VGS, ID = 250 mAdc)

Threshold Temperature Coefficient (Negative)

Static Drain−to−Source On−Resistance (Note 3)

(VGS = 5.0 Vdc, ID = 6.0 Adc)

Static Drain−to−Source On−Voltage (Note 3)

(VGS = 5.0 Vdc, ID = 12 Adc) (VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150°C)

Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 6.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance C

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Transfer Capacitance C

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

VGS = 5.0 Vdc, RG = 9.1 W) (Note 3)

= 30 Vdc, ID = 12 Adc,

Fall Time t

Gate Charge

(VDS = 48 Vdc, ID = 12 Adc,

VGS = 5.0 Vdc) (Note 3)

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 12 Adc, VGS = 0 Vdc) (Note 3)

(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)

Reverse Recovery Time

(IS = 12 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3)

Reverse Recovery Stored Charge Q

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

(BR)DSS

DSS

GSS

GS(th)

DS(on)

d(on)

d(off)

iss

oss

rss

−

62.9

−

mV/°C

−

mAdc

Vdc

−

1.0 10

− − ±100 nAdc

Vdc

1.0

−

1.6

4.2

2.0

−

mV/°C

− 89 104

Vdc

−

0.98

−

0.86

1.50

−

− 9.1 − mhos

− 316 440 pF

− 105 150

− 35 70

− 9.2 20 ns

− 104 210

− 19 40

− 40.5 80

− 7.4 20 nC

− 2.0 −

− 4.0 −

−

0.95

−

0.82

− 35 −

1.2

−

Vdc

− 21 −

− 14 −

− 0.04 −

ORDERING INFORMATION

Device Package Shipping

NTD3055L104G DPAK

75 Units/Rail

(Pb−Free)

NTD3055L104−1G DPAK−3

75 Units/Rail

(Pb−Free)

NTD3055L104T4G DPAK

2500 Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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Page 3

NTD3055L104

TYPICAL CHARACTERISTICS

VGS = 10 V

8 V

6 V

, DRAIN CURRENT (AMPS)

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

5 V

4.5 V

4 V

3.5 V

3 V

4 5 6 7 1.5 2 3 4.5 5 5.5

VDS ≥ 10 V

, DRAIN CURRENT (AMPS)

1 2.5 6

TJ = 25°C

TJ = 100°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

3.5 4

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.32

0.28

0.24

0.20

0.16

0.12

0.08

0.04

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

VGS = 5 V

TJ = 100°C

TJ = 25°C

TJ = −55°C

412

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source Voltage

16 20

0.32

0.28

0.24

0.20

0.16

0.12

0.08

0.04

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

VGS = 10 V

820

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

TJ = 100°C

TJ = 25°C

TJ = −55°C

1612

1.8

1.6

1.4

1.2

(NORMALIZED)

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

ID = 6 A V

= 5 V

−50 50250−25 75 125100

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

10,000

1000

100

, LEAKAGE (nA)

DSS

150 175

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VGS = 0 V

TJ = 150°C

TJ = 100°C

0403020 6010

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

versus Voltage

Page 4

NTD3055L104

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:

tr = Q2 x RG/(VGG − V

tf = Q2 x RG/V

GSP

)

where

VGG = the gate drive voltage, which varies from zero to V

RG = the gate drive resistance

and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when calculating t on−state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

1000

800

iss

600

rss

400

C, CAPACITANCE (pF)

200

10 0 10 15 20 25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS = 0 VVDS = 0 V

rss

Figure 7. Capacitance Variation

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TJ = 25°C

iss

oss

Page 5

NTD3055L104

, GATE−TO−SOURCE VOLTAGE (VOLTS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

VGS = 0 V

ID = 12 A TJ = 25°C

1000

100

t, TIME (ns)

TJ = 150°C

d(off)

d(on)

1 10 100

RG, GATE RESISTANCE (OHMS)

VDS = 30 V ID = 12 A VGS = 5 V

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

TJ = 25°C

, SOURCE CURRENT (AMPS)

0.3

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

0.5 1

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.”

Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (V

) is exceeded and the

DSS

transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (T

J(MAX)

− TC)/(R

qJC

A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For

0.7 0.9

0.80.60.4

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous I

can safely be assumed to

equal the values indicated.

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Page 6

NTD3055L104

SAFE OPERATING AREA

100

VGS = 15 V SINGLE PULSE TC = 25°C

100 ms

1 ms

, DRAIN CURRENT (AMPS)

LIMIT

DS(on)

THERMAL LIMIT

10 ms

PACKAGE LIMIT

0.1

0.1 1 100

10 175

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0

D = 0.5

0.2

0.1

0.05

0.02

(NORMALIZED)

0.01

SINGLE PULSE

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

Figure 13. Thermal Response

10 ms

, SINGLE PULSE DRAIN−TO−SOURCE

t, TIME (s)

AVALANCHE ENERGY (mJ)

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

(pk)

DUTY CYCLE, D = t1/t

(t) = r(t) R

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

- TC = P

J(pk)

(pk)

1100.10.010.0010.00010.00001

ID = 11 A

150

(t)

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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Page 7

12 3

0.005 (0.13) C

DETAIL A

NTD3055L104

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C−01

ISSUE D

GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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Page 8

NTD3055L104

PACKAGE DIMENSIONS

DPAK−3

CASE 369D−01

ISSUE B

−T−

SEATING PLANE

123

D 3 PL

0.13 (0.005) T

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88

E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G H 0.034 0.040 0.87 1.01

J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45

S 0.025 0.040 0.63 1.01

V 0.035 0.050 0.89 1.27

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTD3055L104/D