Page 1
NTD3055-094
Power MOSFET
12 A, 60 V, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
• Lower R
• Lower V
• Lower and Tighter V
• Lower Diode Reverse Recovery Time
• Lower Reverse Recovery Stored Charge
• Pb−Free Packages are Available
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
Drain Current
Total Power Dissipation @ TA = 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Thermal Resistance
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above
the Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq in. pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
DS(on)
DS(on)
SD
= 25°C unless otherwise noted)
J
Rating Symbol Value Unit
− Continuous
− Non−Repetitive (tpv10 ms)
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Derate above 25°C
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH
I
= 11 A, VDS = 60 Vdc)
L(pk)
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
V
V
V
E
R
R
R
DSS
DGR
GS
GS
I
I
I
DM
P
AS
q
q
q
T
60 Vdc
60 Vdc
"20
"30
D
D
D
0.32
2.1
1.5
−55 to
stg
+175
3.13
JC
71.4
JA
JA
L
100
260 °C
Vdc
12
Adc
10
45
Apk
48
61 mJ
W
W/°C
W
W
°C
°C/W
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(BR)DSS
60 V
G
TYP
DS(on)
94 mW
N−Channel
D
S
ID MAXV
12 A
R
MARKING
DIAGRAMS
4
Drain
4
2
1
3
4
1
2
3
55094 = Device Code
Y = Year
WW = Work Week
G = Pb−Free Package
DPAK
CASE 369C
STYLE 2
DPAK−3
CASE 369D
STYLE 2
1
Gate
1
Gate
YWW55094G
2
3
Drain
Source
4
Drain
YWW553094G
3
2
Source
Drain
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 7
1 Publication Order Number:
NTD3055−094/D
Page 2
NTD3055−094
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Characteristic Symbol Min Ty p Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
= 60 Vdc, VGS = 0 Vdc)
(V
DS
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 6.0 Adc)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 12 Adc)
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance C
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
VGS = 10 Vdc, RG = 9.1 W) (Note 3)
(V
= 48 Vdc, ID = 12 Adc,
DD
Fall Time t
Gate Charge
(VDS = 48 Vdc, ID = 12 Adc,
VGS = 10 Vdc) (Note 3)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 12 Adc, VGS = 0 Vdc) (Note 3)
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge Q
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
C
t
d(on)
d(off)
Q
Q
Q
V
t
t
t
FS
iss
oss
rss
r
f
SD
rr
a
b
RR
60
−
68
54.4
−
−
mV/°C
mAdc
Vdc
−
−
−
−
1.0
10
− − ±100 nAdc
Vdc
2.0
−
2.9
6.3
4.0
−
mV/°C
mW
− 84 94
Vdc
−
−
0.85
0.77
1.35
−
− 6.7 − mhos
− 323 450 pF
− 107 150
− 34 70
− 7.7 15 ns
− 32.3 70
− 25.2 50
− 23.9 50
T
1
2
− 10.9 20 nC
− 3.1 −
− 4.2 −
−
−
− 33.1 −
0.94
0.82
1.15
−
Vdc
ns
− 24 −
− 8.9 −
− 0.047 −
mC
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2
Page 3
NTD3055−094
24
20
16
12
8
, DRAIN CURRENT (AMPS)
4
D
I
0
VGS = 10 V
9 V
8 V
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
, DRAIN−TO−SOURCE RESISTANCE (W)
0.02
DS(on)
R
0
0
VGS = 10 V
412
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
7 V
6.5 V
6 V
5.5 V
5 V
4.5 V
21
8
3
TJ = 100°C
TJ = 25°C
TJ = −55°C
16 20
4 5 3.5 4 5 6.5 7 7.5
24
24
VDS ≥ 10 V
20
16
12
8
, DRAIN CURRENT (AMPS)
D
4
I
0
3 4.5 8
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
, DRAIN−TO−SOURCE RESISTANCE (W)
0.02
0
0
DS(on)
R
TJ = 25°C
TJ = 100°C
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 15 V
4
TJ = −55°C
5.5 6
TJ = 100°C
TJ = 25°C
TJ = −55°C
82024
ID, DRAIN CURRENT (AMPS)
1612
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1.8
1.6
1.4
1.2
(NORMALIZED)
0.8
, DRAIN−TO−SOURCE RESISTANCE
0.6
DS(on)
R
ID = 6 A
V
= 10 V
GS
1
−50 50250−25 75 125100
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
1000
100
, LEAKAGE (nA)
10
DSS
I
1
150 175
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3
VGS = 0 V
0403020 6010
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ = 150°C
TJ = 100°C
Figure 6. Drain−to−Source Leakage Current
versus Voltage
50
Page 4
NTD3055−094
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
800
C
iss
600
C
rss
400
200
C, CAPACITANCE (pF)
0
10 0 10 15 20 25
55
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 VVDS = 0 V
C
rss
V
Figure 7. Capacitance Variation
V
GS
DS
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4
TJ = 25°C
C
C
iss
oss
Page 5
NTD3055−094
12
Q
T
V
GS
Q
2
ID = 12 A
TJ = 25°C
4
6
810
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
10
8
Q
6
4
2
0
1
0
212
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
VGS = 0 V
14
TJ = 25°C
12
10
100
t
r
t
d(off)
t
10
t, TIME (ns)
1
1 10 100
f
t
d(on)
RG, GATE RESISTANCE (OHMS)
VDS = 30 V
ID = 12 A
VGS = 10 V
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
8
6
4
, SOURCE CURRENT (AMPS)
S
2
I
0
0.6
0.68 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V
) is exceeded and the
DSS
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
qJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
0.840.76
0.92
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
can safely be assumed to
D
equal the values indicated.
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Page 6
NTD3055−094
SAFE OPERATING AREA
100
VGS = 20 V
SINGLE PULSE
= 25°C
T
C
10 ms
10
100 ms
1 ms
1
, DRAIN CURRENT (AMPS)
D
I
R
LIMIT
DS(on)
THERMAL LIMIT
10 ms
PACKAGE LIMIT
0.1
0.1 1 100
10 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
(NORMALIZED)
0.01
SINGLE PULSE
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
Figure 13. Thermal Response
dc
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
AS
E
t, TIME (ms)
70
ID = 11 A
60
50
50
40
30
20
10
0
25 50 75 100 125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
- TC = P
J(pk)
2
(pk)
1100.10.010.0010.00010.00001
1
R
(t)
q
JC
di/dt
I
S
t
rr
t
t
a
b
TIME
t
p
0.25 I
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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Page 7
ORDERING INFORMATION
NTD3055−094
Device Package Shipping
NTD3055−094 DPAK 75 Units/Rail
NTD3055−094G DPAK
(Pb−Free)
NTD3055−094−1 DPAK−3 75 Units/Rail
NTD3055−094−1G DPAK−3
(Pb−Free)
NTD3055−094T4 DPAK 2500 Tape & Reel
NTD3055−094T4G DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
75 Units/Rail
75 Units/Rail
2500 Tape & Reel
†
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Page 8
NTD3055−094
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE C
NOTES:
SEATING
−T−
PLANE
B
V
S
R
4
A
123
K
F
L
D
2 PL
G
0.13 (0.005) T
C
E
Z
U
J
H
M
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.180 0.215 4.57 5.45
S 0.025 0.040 0.63 1.01
U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
6.20
0.244
5.80
0.228
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2.58
0.101
3.0
0.118
0.063
1.6
SCALE 3:1
6.172
0.243
ǒ
inches
mm
Ǔ
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Page 9
NTD3055−094
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
S
−T−
SEATING
PLANE
F
B
R
4
123
G
A
K
J
D 3 PL
0.13 (0.005) T
C
E
H
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
Z
A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
0.090 BSC 2.29 BSC
G
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NTD3055−094/D
9
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