Datasheet ntd24n06 Datasheet

NTD24N06

Power MOSFET
60 Volt, 24 Amp

N−Channel DPAK

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Features

• Pb−Free Packages are Available

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage

− Continuous

− Non−repetitive (tpv10 ms)

Drain Current

− Continuous @ TA = 25°C, TJ = 150°C

− Continuous @ TA = 25°C, TJ = 175°C

− Continuous @ TA = 100°C, TJ = 175°C

− Single Pulse (tpv10 ms), TJ = 175°C

Total Power Dissipation @ T

Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
L = 1.0 mH, IL(pk) = 18 A, VDS = 60 Vdc)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.

2. When surface mounted to an FR−4 board using the minimum recommended
pad size.

= 25°C unless otherwise noted)

J

Rating Symbol Value Unit

stg

60 Vdc
60 Vdc

"20
"30

24
27
19
80

62.5

0.42

1.88

1.36

− 55 to
+175

162 mJ

2.4
80

110
260 °C

Vdc

Adc
Adc
Adc
Apk

W

W/°C

W
W

°C

°C/W

= 25°C

A

V

V
V

E

R
R
R

DSS
DGR

GS
GS

I
I
I

I

DM

P

AS

q
q
q

T

D
D
D

D

JC
JA
JA

L

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(BR)DSS

60 V

G

TYP

DS(on)

32 mW

N−Channel

D

S

ID MAXV

24 A

R

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Gate

Gate

1

1

Drain

24

YWW

2

Drain

4

Drain

24

YWW

2

Drain

N06G

3
Source

N06G

3
Source

4

2

1

3

DPAK

CASE 369C

(Surface Mount)

STYLE 2

4

1

2

3

DPAK

CASE 369D

(Straight Lead)

STYLE 2

Y = Year
WW = Work Week
24N06 = Device Code
G = Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2005

August, 2005 − Rev. 4

1 Publication Order Number:

NTD24N06/D

NTD24N06

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

(VGS = 0 Vdc, ID = 250 mAdc)

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I

V

(BR)DSS

I

DSS

GSS

60

−

71.1

70.4

−

−

mV/°C

mAdc

Vdc

−

−

−

−

1.0
10

− − ±100 nAdc

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(VDS = VGS, ID = 250 mAdc)

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)

(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 10 Vdc, ID = 12 Adc)

Static Drain−to−Source On−Resistance (Note 3)

(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 24 Adc)
(VGS = 10 Vdc, ID = 12 Adc, TJ = 150°C)

Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 12 Adc) g

V

GS(th)

R

DS(on)

V

DS(on)

FS

2.0

−

3.03

7.0

4.0

−

mV/°C

mW

Vdc

−

−

32
32

42

−
Vdc

−

−

−

0.8

0.8

0.7

1.15

−

−

− 15 − mhos

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance C

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Transfer Capacitance C

C

iss
oss
rss

− 846 1200 pF

− 252 350

− 68 95

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

(V

= 30 Vdc, ID = 24 Adc,

Rise Time t
Turn−Off Delay Time t

DD

VGS = 10 Vdc,

RG = 9.1 W) (Note 3)

Fall Time t
Gate Charge

(VDS = 48 Vdc, ID = 24 Adc,

VGS = 10 Vdc) (Note 3)

t

d(on)

d(off)

Q
Q
Q

− 10 20 ns

r

− 24 50

− 25 50

f

T
1
2

− 27 60

− 24 48 nC

− 5.0 −

− 11.5 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3)

(IS = 24 Adc, VGS = 0 Vdc)

(IS = 24 Adc, VGS = 0 Vdc, TJ = 150°C)

Reverse Recovery Time

(IS = 24 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)

Reverse Recovery Stored Charge Q

V

SD

t

rr

t

a

t

b
RR

−

−

−

0.95

1.0

0.89

1.15

− 49 −

− 35 −

− 13 −

− 0.096 −

−

Vdc

−
ns

mC

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

ORDERING INFORMATION

Device Package Shipping

NTD24N06 DPAK 75 Units / Rail
NTD24N06G DPAK

75 Units / Rail

(Pb−Free)
NTD2406−1 DPAK (Straight Lead) 75 Units / Rail
NTD2406−1G DPAK (Straight Lead)

75 Units / Rail

(Pb−Free)
NTD24N06T4 DPAK 2500 Tape & Reel
NTD24N06T4G DPAK

2500 Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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2

NTD24N06

0

0

50

VGS = 10 V

40

30

20

10

, DRAIN CURRENT (AMPS)

D

I

0

04

9 V

8 V

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

7 V

6 V

5.5 V

5 V

4.5 V

21

3

50

VDS ≥ 10 V

40

30

20

TJ = 25°C

10

, DRAIN CURRENT (AMPS)

D

I

0

23 8

TJ = 100°C

45

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.08

0.06

0.04

0.02

VGS = 10 V

TJ = 100°C

TJ = 25°C

TJ = −55°C

0.08

0.06

0.04

0.02

VGS = 15 V

TJ = 100°C

TJ = 25°C

TJ = −55°C

TJ = −55°C

67

, DRAIN−TO−SOURCE RESISTANCE (W)

0

DS(on)

0

R

10 40

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source Voltage

2

ID = 12 A
V

= 10 V

1.8

1.6

1.4

1.2

(NORMALIZED)

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.6

DS(on)

R

GS

1

−50 50250−25 75 125100
TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

, DRAIN−TO−SOURCE RESISTANCE (W)

0

3020

50

DS(on)

R

0

10 40

ID, DRAIN CURRENT (AMPS)

3020

5

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

50

150 175

10000

1000

100

, LEAKAGE (nA)

DSS

I

VGS = 0 V

TJ = 150°C

TJ = 100°C

10

1

0403020 6

10

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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NTD24N06

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

2400

C

2000

1600

1200

C, CAPACITANCE (pF)

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

iss

C

rss

800

400

0

10 0 10 15 20 25

55

V

VGS = 0 VVDS = 0 V

C

rss

GS

Figure 7. Capacitance Variation

V

DS

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4

TJ = 25°C

C

iss

C

oss

NTD24N06

0

V

, GATE−TO−SOURCE VOLTAGE (VOLTS

12

Q

T

V

GS

Q

2

ID = 24 A
TJ = 25°C

12

16

20 24

GS

10

8

Q

1

6

4

2

0

0

48 28

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

24

VGS = 0 V
TJ = 25°C

20

16

1000

100

t

t

t, TIME (ns)

d(off)

10

1

11010

r

t

t

d(on)

f

RG, GATE RESISTANCE (OHMS)

VDS = 30 V
ID = 24 A
VGS = 10 V

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

12

8

4

, SOURCE CURRENT (AMPS)

S

I

0

0.6

0.68 0.76 1

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”

Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V

) is exceeded and the

DSS

transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (T

J(MAX)

− TC)/(R

qJC

).

A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For

0.84 0.92

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance w i th i ndust ry c us tom.
The energy rating must b e derated for temperature as shown
in the accompanying graph (Fi gure 12). Maxi mum energy a t
currents below rated c onti nuous I

can safely be assumed to

D

equal the values indicated.

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5

NTD24N06

E

100

I

, DRAIN CURRENT (AMPS)

5

200

SAFE OPERATING AREA

VGS = 20 V
SINGLE PULSE
TC = 25°C

10

100 ms

10 ms

1 ms

1

R

LIMIT

D

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

10 ms

0.1

0.1 1 100

10 17

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0

D = 0.5

0.2

0.1

0.05

0.1

0.02

(NORMALIZED)

0.01

SINGLE PULSE

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

Figure 13. Thermal Response

dc

160

120

80

40

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURC

0

AS

E

P

(pk)

t

1

DUTY CYCLE, D = t1/t

t, TIME (ms)

ID = 18 A

25 50 75 100 125

150

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

R

(t) = r(t) R

q

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

t

2

2

T

J(pk)

− TC = P

q

(pk)

1.0E+00 1.0E+011.0E−011.0E−021.0E−031.0E−041.0E−05

JC

1

R

(t)

q

JC

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

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6

NTD24N06

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE O

SEATING

−T−

PLANE

B

V

S

R

4

A

123

K

F

L

D

2 PL

G

0.13 (0.005) T

C

E

Z

U

J

H

M

NOTES:

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.180 0.215 4.57 5.45
S 0.025 0.040 0.63 1.01
U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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7

NTD24N06

PACKAGE DIMENSIONS

DPAK

CASE 369D−01

ISSUE B

V

S

−T−

SEATING
PLANE

F

B
R

4

123

G

A

K

D 3 PL

0.13 (0.005) T

C

E

J

H

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

Z

A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88

E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G
H 0.034 0.040 0.87 1.01

J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45

S 0.025 0.040 0.63 1.01

V 0.035 0.050 0.89 1.27

Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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NTD24N06/D

8