Page 1
NTB35N15
l
l
Power MOSFET
37 Amps, 150 Volts
N−Channel Enhancement−Mode D2PAK
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• I
and R
DSS
• Mounting Information Provided for the D
Specified at Elevated Temperature
DS(on)
2
PAK Package
• Pb−Free Packages are Available
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Drain−to−Source Voltage (RGS = 1.0 M)
Gate−to−Source Voltage
Drain Current − Continuous @ TA = 25°C
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
I
= 21.6 A, L = 3.0 mH, RG = 25 )
L(pk)
Thermal Resistance
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu. Area 0.412 in2).
2. Pulse Test: Pulse Width = 10 s, Duty Cycle = 2%.
− Continuous
− Non−Repetitive (tpv10 ms)
− Continuous @ TA = 100°C
− Pulsed (Note 2)
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
= 25°C unless otherwise noted)
J
Rating Symbol Value Unit
D
stg
JC
JA
JA
L
150 Vdc
150 Vdc
"20
"40
37
23
111
178
1.43
2.0
− 55 to
+150
700 mJ
0.7
62.5
50
260 °C
Vdc
Adc
W
W/°C
W
°C
°C/W
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
E
AS
R
R
R
T
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37 AMPERES, 150 VOLTS
50 m @ VGS = 10 V
N−Channel
D
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
35N15G
AYWW
1
Gate
Drain
3
2
Source
Drain
†
50 Units/Rail
800 Tape & Ree
4
1
2
3
D2PAK
CASE 418B
STYLE 2
35N15 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device Package Shipping
NTB35N15 D2PAK 50 Units/Rail
NTB35N15G D2PAK
NTB35N15T4 D2PAK 800 Tape & Ree
NTB35N15T4G D2PAK
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(Pb−Free)
(Pb−Free)
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 5
1 Publication Order Number:
NTB35N15/D
Page 2
NTB35N15
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 125°C)
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = V
ID = 250 Adc)
GS,
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID = 18.5 Adc)
(VGS = 10 Vdc, ID = 18.5 Adc, TJ = 125°C)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 18.5 Adc)
Forward Transconductance (VDS = 10 Vdc, ID = 18.5 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance C
SWITCHING CHARACTERISTICS (Notes 3 & 4)
(V
Turn−On Delay Time
Rise Time t
= 120 Vdc, ID = 37 Adc,
DD
VGS = 10 Vdc,
RG = 9.1 )
Turn−Off Delay Time t
Fall Time t
Total Gate Charge
Gate−to−Source Charge Q
(VDS = 120 Vdc, ID = 37 Adc,
VGS = 10 Vdc)
Gate−to−Drain Charge Q
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage (IS = 37 Adc, VGS = 0 Vdc)
(IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time (IS = 37 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge Q
3. Pulse Test: Pulse Width =300 s max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
C
t
d(on)
d(off)
Q
V
t
t
t
FS
iss
oss
rss
r
f
tot
gs
gd
SD
rr
a
b
RR
150
−
−
240
−
−
mV/°C
Adc
−
−
−
−
5.0
50
− − ± 100 nAdc
2.0
−
−
−
2.9
−8.56
4.0
−
0.042−0.050
0.120
mV/°C
− 1.55 1.78
− 26 − mhos
− 2275 3200
− 450 650
− 90 175
− 20 35
− 125 225
− 90 175
− 120 210
− 70 100
− 14 −
− 32 −
−
−
1.00
0.88
1.5
−
− 170 −
− 112 −
− 58 −
− 1.14 −
Vdc
Vdc
Vdc
pF
ns
nC
Vdc
ns
C
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NTB35N15
70
70
I
, DRAIN CURRENT (AMPS)
R
, DRAIN−TO−SOURCE RESISTANCE (
)
0
R
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
0
60
V
50
40
30
20
D
10
0
0.1
0.08
0.06
0.04
VGS = 10 V
= 9 V
GS
V
= 5.5 V
GS
V
= 8 V
GS
V
= 7 V
GS
V
= 6 V
GS
TJ = 25°C
V
GS
V
GS
V
GS
89
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
VGS = 10 V
TJ = 100°C
TJ = 25°C
= 5 V
= 4.5 V
= 4 V
60
50
40
30
20
, DRAIN CURRENT (AMPS)
D
I
10
1076543210
0
0.055
0.05
0.045
0.04
VDS ≥ 10 V
TJ = 100°C
TJ = 25°C
TJ = −55°C
765432
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
TJ = 25°C
VGS = 10 V
VGS = 15 V
0.02
TJ = −55°C
0.035
, DRAIN−TO−SOURCE RESISTANCE ()
DS(on)
0
ID, DRAIN CURRENT (AMPS)
50403020100
7060
Figure 3. On−Resistance versus Drain Current
and Temperature
2.5
2.25
2.0
1.75
ID = 18.5 A
VGS = 10 V
0.03
DS(on)
R
10,000
1000
403020100
50
60
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 150°C
7
1.5
1.25
1.0
0.75
, LEAKAGE (nA)
100
DSS
I
TJ = 100°C
0.5
0.25
0
DS(on),
1501251007550250−25−50
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
10
504030
7060 15
80
10090 110 120 130 140
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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NTB35N15
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
6000
5000
C
iss
4000
3000
C
rss
2000
C, CAPACITANCE (pF)
1000
0
10 0 10 15 20 25
55
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 VVDS = 0 V
C
rss
V
Figure 7. Capacitance Variation
V
GS
DS
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4
TJ = 25°C
C
iss
C
oss
Page 5
NTB35N15
12
Q
T
Q
2
ID = 37 A
TJ = 25°C
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
10
V
DS
8
Q
1
6
4
2
0
0
20 7040
10 5030 60
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
40
35
30
25
VGS = 0 V
TJ = 25°C
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS,
V
1000
VDD = 75 V
ID = 37 A
VGS = 10 V
t
d(off)
100
t, TIME (ns)
t
d(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
t
f
t
r
120
100
80
V
GS
60
40
20
0
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
20
15
10
, SOURCE CURRENT (AMPS)
S
I
5
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V
) is exceeded and the
DSS
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
JC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
10.2
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance w i th i ndust ry c us tom.
The energy rating must b e derated for temperature as shown
in the accompanying graph (Fi gure 12). Maxi mum energy a t
currents below rated c onti nuous I
can safely be assumed to
D
equal the values indicated.
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NTB35N15
SAFE OPERATING AREA
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10
, DRAIN CURRENT (AMPS)
1
D
I
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1 1.0 100
10 150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.1
0.05
(NORMALIZED)
0.02
0.01
SINGLE PULSE
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
700
600
10 s
100 s
1 ms
10 ms
dc
1000
500
400
300
200
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
100
AS
E
0
25 50 75 100 125
Figure 12. Maximum Avalanche Energy versus
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
t, TIME (s)
Figure 13. Thermal Response
ID = 21.6 A
TJ, STARTING JUNCTION TEMPERATURE (°C)
Starting Junction Temperature
R
(t) = r(t) R
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
− TC = P
J(pk)
2
(pk)
JC
1
R
(t)
JC
1.0 100.10.010.0010.00010.00001
di/dt
I
S
t
rr
t
t
a
b
TIME
t
p
0.25 I
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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NTB35N15
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
−B−
4
231
−T−
SEATING
PLANE
VARIABLE
CONFIGURATION
ZONE
G
M
S
D
3 PL
0.13 (0.005) T
R
L
M
C
E
V
W
A
K
W
J
H
M
M
B
N P
U
L
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
L 0.052 0.072 1.32 1.83
M 0.280 0.320 7.11 8.13
N 0.197 REF 5.00 REF
P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
L
MILLIMETERSINCHES
M
F
VIEW W−W VIEW W−W VIEW W−W
123
F
F
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
17.02
0.67
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1.016
3.05
0.12
SCALE 3:1
0.04
mm
ǒ
inches
5.08
0.20
Ǔ
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NTB35N15
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NTB35N15/D
8
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