Datasheet NTB30N20 Datasheet (ON Semiconductor)

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Page 1

NTB30N20

l l

Power MOSFET 30 Amps, 200 Volts

N−Channel Enhancement−Mode D2PAK

Features

• Source−to−Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Avalanche Energy Specified

• I

and R

DSS

• Mounting Information Provided for the D

Specified at Elevated Temperature

DS(on)

PAK Package

• Pb−Free Packages are Available

Typical Applications

• PWM Motor Controls

• Power Supplies

• Converters

MAXIMUM RATINGS (T

Drain−to−Source Voltage V Drain−to−Source Voltage (RGS = 1.0 MW) Gate−to−Source Voltage

− Continuous

− Non−Repetitive (tpv10 ms)

Drain Current − Continuous @ TA 25°C

− Continuous @ TA 100°C

− Pulsed (Note 2)

Total Power Dissipation @ TA = 25°C Derate above 25°C

Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range TJ, T

Single Drain−to−Source Avalanche Energy, Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL(pk) = 20 A, L = 3.0 mH, RG = 25 W)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient

− Junction−to−Ambient (Note 1)

Maximum Lead Temperature for Soldering Purposes for 10 seconds

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).

2. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.

= 25°C unless otherwise noted)

Rating Symbol Value Unit

stg

JC JA JA

200 Vdc 200 Vdc

"30 "40

30 22 90

214

1.43

2.0

− 55 to +175

450

0.7

62.5

260 °C

Vdc

Adc

W/°C

°C

°C/W

DSS

DGR

GSM

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DSS

200 V

TYP ID MAX

DS(ON)

68 mW @ VGS = 10 V

N−Channel

30 A

MARKING DIAGRAM

& PIN ASSIGNMENT

Gate

Drain

30N20G AYWW

Drain

Source

D2PAK

CASE 418B

STYLE 2

30N20 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

NTB30N20 D2PAK 50 Units/Rail NTB30N20G D2PAK

(Pb−Free) NTB30N20T4 D2PAK 800 Tape & Ree NTB30N20T4G D2PAK

(Pb−Free) †For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

50 Units/Rail

800 Tape & Ree

†

August, 2005 − Rev. 4

1 Publication Order Number:

NTB30N20/D

Page 2

NTB30N20

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 mAdc)

Temperature Coefficient (Positive) Zero Gate Voltage Collector Current

(VGS = 0 Vdc, VDS = 200 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 200 Vdc, TJ = 175°C)

Gate−Body Leakage Current (VGS = ± 30 Vdc, VDS = 0) I

ON CHARACTERISTICS

Gate Threshold Voltage

VDS = V

ID = 250 mAdc)

GS,

Temperature Coefficient (Negative) Static Drain−to−Source On−State Resistance

(VGS = 10 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 175°C)

Drain−to−Source On−Voltage

(VGS = 10 Vdc, ID = 30 Adc)

Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)

(VDS = 160 Vdc, VGS = 0 Vdc, f = 1.0 MHz)

Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C

SWITCHING CHARACTERISTICS (Notes 3 & 4)

Turn−On Delay Time

Rise Time t

= 100 Vdc, ID = 18 Adc,

VGS = 5.0 Vdc, RG = 2.5 W)

Turn−Off Delay Time t

= 160 Vdc, ID = 30 Adc,

VGS = 10 Vdc, RG = 9.1 W)

Fall Time t

Gate Charge

(VDS = 160 Vdc, ID = 30 Adc,

VGS = 10 Vdc)

(VDS = 160 Vdc, ID = 18 Adc,

VGS = 5.0 Vdc)

BODY−DRAIN DIODE RATINGS (Note 3)

Forward On−Voltage (IS = 30 Adc, VGS = 0 Vdc)

(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)

Reverse Recovery Time

(IS = 30 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/ms)

Reverse Recovery Stored Charge Q

3. Indicates Pulse Test: P. W. = 300 ms max, Duty Cycle = 2%.

4. Switching characteristics are independent of operating junction temperature.

(BR)DSS

DSS

GSS

GS(th)

DS(on)

d(on)

d(off)

t t t

iss

oss

rss

tot

rr a b

200

−

307

−

mV/°C

mAdc

Vdc

−

5.0

125

− − ± 100 nAdc

Vdc

2.0

−

2.9

−8.9

0.068

0.067

0.200

4.0

−

0.081

0.080

0.240

mV/°C

Vdc

− 2.0 2.5

− 20 − Mhos

− 2335 − pF

−

380 148

−

− 75 −

−

10 12

20 70

40 82

24 88

75 48

20 16

−

100

−

− 32 −

−

0.91

0.80

1.1

−

Vdc

− 230 −

− 140 −

− 85 −

− 1.85 −

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NTB30N20

, DRAIN CURRENT (AMPS)

, DRAIN−TO−SOURCE RESISTANCE (

)

DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

0.15

0.2

0.1

VGS = 10 V

9 V

7 V

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

6 V

TJ = 25°C

8 V

5 V

4 V

Figure 1. On−Region Characteristics

VGS = 10 V

TJ = 100°C

TJ = 25°C

VDS ≥ 10 V

, DRAIN CURRENT (AMPS)

106420

080

TJ = 25°C

TJ = 100°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

6420

Figure 2. Transfer Characteristics

0.1 TJ = 25°C

0.09

0.08

0.07

VGS = 10 V

VGS = 15 V

0.05

DS(on)

Figure 3. On−Resistance versus Drain Current

2.5

1.5

0.5

DS(on),

ID = 15 A VGS = 10 V

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

TJ = −55°C

3525155

ID, DRAIN CURRENT (AMPS)

and Temperature

Temperature

0.06

, DRAIN−TO−SOURCE RESISTANCE (W)

5545

0.05

DS(on)

ID, DRAIN CURRENT (AMPS)

453525155

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

100000

1751251007550250−25−50

10000

, LEAKAGE (nA)

DSS

1000

100

VGS = 0 V

TJ = 175°C

TJ = 100°C

4020

60 20

808100 120 140

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

160 180150

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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NTB30N20

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following: tr = Q2 x RG/(VGG − V tf = Q2 x RG/V

GSP

)

where VGG = the gate drive voltage, which varies from zero to V

RG = the gate drive resistance and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when calculating t on−state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

6000

5000

4000

3000

2000

C, CAPACITANCE (pF)

1000

iss

rss

05 510 20

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE

Figure 7. Capacitance Variation

VGS = 0 VVDS = 0 V

rss

015

(VOLTS)

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TJ = 25°C

iss

oss

Page 5

1000

180

, GATE−TO−SOURCE VOLTAGE (VOLTS)

NTB30N20

150

120

DS,

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

100

t, TIME (ns)

VDD = 160 V ID = 30 A VGS = 10 V

d(off)

d(on)

ID = 30 A TJ = 25°C

20 7040

10 5030 60

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

VGS = 0 V

TJ = 25°C

, SOURCE CURRENT (AMPS)

Figure 10. Diode Forward Voltage versus Current

0.6 0.7 0.8 0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

11010

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

10.5

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.”

Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (V

) is exceeded and the

DSS

transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (T

J(MAX)

− TC)/(R

qJC

A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For

SAFE OPERATING AREA

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance w i th i ndust ry c us tom. The energy rating must b e derated for temperature as shown in the accompanying graph (Fi gure 12). Maxi mum energy a t currents below rated c onti nuous I equal the values indicated.

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can safely be assumed to

Page 6

NTB30N20

1000

, DRAIN CURRENT (AMPS)

500

SAFE OPERATING AREA

VGS = 20 V SINGLE PULSE TC = 25°C

100

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

0.1

0.1 1.0 100

10 17

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0 D = 0.5

0.2

0.1

0.05

(NORMALIZED)

0.02

0.01

SINGLE PULSE

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

400

10 ms

100 ms

1 ms

300

200

10 ms

1000

100

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURC

25 50 75 100 125

Figure 12. Maximum Avalanche Energy versus

(pk)

DUTY CYCLE, D = t1/t

t, TIME (ms)

Figure 13. Thermal Response

ID = 30 A

150

TJ, STARTING JUNCTION TEMPERATURE (°C)

Starting Junction Temperature

(t) = r(t) R

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

− TC = P

J(pk)

(pk)

1.0 100.10.010.0010.00010.00001

(t)

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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Page 7

NTB30N20

PACKAGE DIMENSIONS

D2PAK

CASE 418B−04

ISSUE J

−B−

231

−T−

SEATING PLANE

VARIABLE CONFIGURATION ZONE

3 PL

0.13 (0.005) T

N P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.035 0.51 0.89 E 0.045 0.055 1.14 1.40 F 0.310 0.350 7.87 8.89 G 0.100 BSC 2.54 BSC H 0.080 0.110 2.03 2.79 J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79 L 0.052 0.072 1.32 1.83 M 0.280 0.320 7.11 8.13 N 0.197 REF 5.00 REF P 0.079 REF 2.00 REF R 0.039 REF 0.99 REF S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

VIEW W−W VIEW W−W VIEW W−W

123

SOLDERING FOOTPRINT*

8.38

0.33

10.66

0.42

17.02

0.67

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

1.016

3.05

0.12

SCALE 3:1

0.04

inches

5.08

0.20

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Page 8

NTB30N20

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NTB30N20/D