Datasheet NTP27N06, NTB27N06 Datasheet (ON Semiconductor)

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NTP27N06, NTB27N06

Power MOSFET
27 Amps, 60 Volts

N–Channel TO–220 and D2PAK

Designed for low voltage, high speed switching applications in

power supplies, converters, power motor controls and bridge circuits.

Features

• Higher Current Rating

• Lower R

• Lower V

• Lower Capacitances

T ypical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 10 MΩ) V
Gate–to–Source Voltage

Drain Current

Total Power Dissipation @ TA = 25°C

Operating and Storage Temperature Range TJ, T

Single Pulse Drain–to–Source Avalanche

Thermal Resistance – Junction–to–Case R
Maximum Lead Temperature for Soldering

DS(on)
DS(on)

= 25°C unless otherwise noted)

C

Rating Symbol Value Unit

– Continuous
– Non–Repetitive (tp10 ms)

– Continuous @ TA = 25°C
– Continuous @ TA 100°C
– Single Pulse (tp10 µs)

Derate above 25°C

Energy – Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
L = 0.3 mH, IL(pk) = 27 A,VDS = 60 Vdc)

Purposes, 1/8″ from case for 10 seconds

DSS

DGR

V

GS

V

GS

I

D

I

D

I

DM
P

E

AS

θJC

T

60 Vdc
60 Vdc

20
30

27
15
80

stg

88.2

0.59WW/°C

–55 to

+175

109 mJ

1.7 °C/W

260 °C

D

L

Vdc

Adc

Apk

°C

1

Gate

2

1

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27 AMPERES

60 VOLTS

R

DS(on)

N–Channel

G

4

TO–220AB

CASE 221A

STYLE 5

3

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

NTx27N06
LLYWW

3
Source

2

Drain

= 46 mΩ

D

S

1

2

3

D2PAK

CASE 418B

STYLE 2

4

Drain

NTx27N06
LLYWW

2

1

Drain

Gate

NTx27N06 = Device Code
x = B or P
LL = Location Code
Y = Year
WW = Work Week

4

3
Source

 Semiconductor Components Industries, LLC, 2001

August, 2001 – Rev. 2

ORDERING INFORMATION

Device Package Shipping

NTP27N06 TO–220AB 50 Units/Rail
NTB27N06 D2PAK 50 Units/Rail
NTB27N06T4 D2PAK 800/Tape & Reel

1 Publication Order Number:

NTP27N06/D

NTP27N06, NTB27N06

)

f

MHz)

R

G

9.1 Ω) (Note 1.)
)

V

GS

Vdc) (Note 1.)

)

dIS/dt

100 A/µs) (Note 1.)

ELECTRICAL CHARACTERISTICS (T

Characteristic

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Note 1.)

(VGS = 0 Vdc, ID = 250 µAdc)

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 1.)

Gate Threshold Voltage (Note 1.)

(VDS = VGS, ID = 250 µAdc)

Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (Note 1.)

(VGS = 10 Vdc, ID = 13.5 Adc)

Static Drain–to–Source On–Resistance (Note 1.)

(VGS = 10 Vdc, ID = 27 Adc)
(VGS = 10 Vdc, ID = 13.5 Adc, TJ = 150°C)

Forward Transconductance (Note 1.) (VDS = 7.0 Vdc, ID = 6.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2.)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 27 Adc, VGS = 0 Vdc, TJ = 150°C)

Reverse Recovery Time

Reverse Recovery Stored Charge Q

1. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

2. Switching characteristics are independent of operating junction temperature.

= 25°C unless otherwise noted)

J

(VDS = 25 Vdc, VGS = 0 Vdc,

(IS = 27 Adc, VGS = 0 Vdc) (Note 1.)

f = 1.0 MHz

= 1.0

(VDD = 30 Vdc, ID = 27 Adc,

VGS = 10 Vdc,

RG = 9.1 Ω) (Note 1.)

(VDS = 48 Vdc, ID = 27 Adc,

V

= 10 Vdc) (Note 1.

= 10

(IS = 27 Adc, VGS = 0 Vdc,
dI

/dt = 100 A/µs) (Note 1.

=

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

V

SD

t

rr

t

a

t

b

RR

60

–

–
–

– – ±100 nAdc

2.0
–

– 37.5 46

–
–

– 13.2 – mhos

– 725 1015 pF
– 213 300
– 58 120

– 13.6 30 ns
– 62.7 125
– 26.6 60
– 70.4 140
– 21.2 30 nC
– 5.6 –
– 7.3 –

–
–

– 42 –
– 26 –
– 16 –
– 0.07 – µc

70

79.4

–
–

2.8

6.9

1.05

2.12

1.05

0.93

–
–

1.0
10

4.0

–

1.5

–

1.25
–

mV/°C

mV/°C

Vdc

µAdc

Vdc

m

Vdc

Vdc

ns

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2

NTP27N06, NTB27N06

56
48

40

32

24

16

, DRAIN CURRENT (AMPS)

D

8

I

0

0

VGS = 10 V

9 V

8 V

21

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

7.5 V

3

45

7 V

6.5 V

6 V

5.5 V

5 V

4.5 V

6

56

VDS  10 V

48

40

32

24

16

, DRAIN CURRENT (AMPS)

D

8

I

0

2.6 3.4 8.2

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.095
VGS = 10 V

0.085

0.075

0.065

0.055

0.045

0.035

0.025

, DRAIN–TO–SOURCE RESISTANCE (Ω)

0.015

032241684056

DS(on)

R

TJ = 100°C

TJ = 25°C

TJ = –55°C

48

ID, DRAIN CURRENT (AMPS)

0.095

0.085

0.075

0.065

0.055

0.045

0.035

0.025

, DRAIN–TO–SOURCE RESISTANCE (Ω)

0.015

DS(on)

R

VGS = 15 V

032241684056

TJ = 25°C

TJ = 100°C

TJ = –55°C

4.2 5 5.8 6.6 7.4

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

TJ = 100°C

TJ = 25°C

TJ = –55°C

48

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus

Gate–to–Source Voltage

2.2
ID = 13.5 A

VGS = 10 V

1.8

1.4

1

0.6

–50 50250–25 75 100

, DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)

DS(on)

R

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

10000

1000

100

, LEAKAGE (nA)

10

DSS

I

1

175150125

04050302010 60

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3

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 100°C

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–to–Source Leakage Current

versus V oltage

NTP27N06, NTB27N06

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
times may be approximated by the following:

tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

) can be made from a

G(AV)

. Therefore, rise and fall

SGP

)

)]

GSP

)

GSP

GG

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when
calculating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

1800
1600

C

1400
1200
1000

C, CAPACITANCE (pF)

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

iss

C

rss

800
600
400
200

0

10 0 10 15 20 25

55

VGS = 0 VVDS = 0 V

C

rss

V

GSVDS

Figure 7. Capacitance Variation

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4

TJ = 25°C

C

iss

C

oss

NTP27N06, NTB27N06

12

Q

T

Q

2

ID = 27 A
TJ = 25°C

40

, GATE–TO–SOURCE VOLTAGE (VOLTS)

GS

V

10

8

Q

1

6

4

2

0

0

10 60

20 5030 70

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

60

VGS = 0 V
TJ = 25°C

50

40

1000

V

GS

100

t

r

t, TIME (ns)

10

t

d(on)

1

1 10 100

RG, GATE RESISTANCE (Ω)

t

f

t

d(off)

VDS = 30 V
ID = 27 A
VGS = 10 V

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

30

20

10

, SOURCE CURRENT (AMPS)

S

I

0

0.6

0.68 0.76 1

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”

Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V

) is exceeded and the

DSS

transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (T

J(MAX)

– TC)/(R

θJC

).

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For

0.84

0.92

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum e ner gy a t
currents below rated continuous ID can safely be assumed t o
equal the values indicated.

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5

NTP27N06, NTB27N06

SAFE OPERATING AREA

100

VGS = 20 V
SINGLE PULSE
TC = 25°C

10 µs

10

, DRAIN CURRENT (AMPS)

D

I

1

0.1 1 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

100 µs

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1 ms

10 ms

10 175

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1

D = 0.5

0.2

dc

200
175
150
125
100

75
50
25

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN–TO–SOURCE

0

AS

25 50 75 100 125

E

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

ID = 27 A

150

0.1

0.05

RESISTANCE (NORMALIZED)

SINGLE PULSE

0.1

r(t), EFFECTIVE TRANSIENT THERMAL

0.01

0.001
t, TIME (s)

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

1100.10.010.0001

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NTP27N06, NTB27N06

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection

0.33

8.38

0.42

10.66

17.02

0.63

interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.

0.08

2.032

1.016

0.12

3.05

0.24

6.096

0.04

inches

mm

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7

NTP27N06, NTB27N06

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1 : 1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
typical stencil for the DPAK and D2PAK packages. The

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.

SOLDER PASTE
OPENINGS

STENCIL

Figure 15. Typical Stencil for DPAK and

D2PAK Packages

• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied
during cooling.

* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.

* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.

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8

NTP27N06, NTB27N06

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1
“RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT
SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 16. Typical Solder Heating Profile

MAX

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9

–T–

SEATING
PLANE

–B–

G

NTP27N06, NTB27N06

PACKAGE DIMENSIONS

D2PAK

CASE 418B–03

ISSUE D

C

E

V

4

A

231

S

K

J

3 PL

D

0.13 (0.005) T

M

M

B

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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10

NTP27N06, NTB27N06

PACKAGE DIMENSIONS

TO–220

CASE 221A–09

ISSUE AA

SEATING

–T–

PLANE

B

4

Q

123

F

T

A

U

C

S

H

K

Z

L

V

R
J

G

D

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 --- 1.15 ---
Z --- 0.080 --- 2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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11

NTP27N06, NTB27N06

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

http://onsemi.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

NTP27N06/D

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