Datasheet NT6868A, NT6868AH Datasheet (NOVATEK)

Features

NT6868A

Keyboard Controller

n Built-in 6502 8-bit CPU
n 2 MHz CPU operation frequency
n 4K bytes of ROM
n 128 bytes of SRAM
n One 8-bit programmable base timer with

1 - 256 µsec interval

n 29 programmable bi-directional I/O pins
n 3 LED direct sink pins with internal serial resistors

General Description

NT6868A is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM, and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base

Pin Configuration

GND

NC

DATA

CLK

P30
P31
P32
P33
P34

RESET

P00
P01
P02
P03

P05
P06
P07
P10
P11

1
2
3
4
5
6
7
8

NT6868A

9
10
11
12
13
14
15
16 25
17
18
19
20

OSCI

40
39

R/OSCO
VDD

38

LED2

37

LED1

36

LED0

35
34

P27
P26

33

P25

32
31

P24

30

P23

29

P22

28

P21

27

P20
P17P04

26

P16

24

P15

23

P14

22

P13
P12

21

n Mask optional for built-in RC oscillator with an

external resistor or external ceramic resonator applied

n Watch-dog timer
n Built-in power-on reset
n Built-in low voltage reset
n CMOS technology for low power consumption
n Available in 40 pin DIP package and 40 pad CHIP

FORM

timer. Additionally, it includes a built-in low voltage
reset, a 4MHz RC oscillator that requires only a resistor
externally applied or a 4MHz ceramic resonator, and a
watch-dog timer that prevents system standstill.

Pad Configuration

P

P

P

P

P

P

P

P

P

P

1

0

0

0

7

6

16

15

14

13

12

11

10

9

8

7

6 5 4 3 2

LED0

LED1

1

1

1

1

1

1

7

6

5

4

26 25 24 23 22 21 20 19 18 17

27

P20

28

P21

29

P22

30

P23

31

P24

32

P25

33

P26

34

P27

35

36

1

3

2

1

NT6868AH

40393837

1

P05

P04

P03

P02

P01

P00

RESET

P34

P33

P32

P31

G

O

R

V

L

D

S

/

E

D

C

O

D
2

I

S
C
O

NCD

C
N
D

P

A

L

3

T

K

0

A

1 V2.1

Block Diagram

TIMING GENERATOR

(RC OSC/CERAMIC RESONATOR:

4MHz)

4K BYTES

ROM

NT6868A

CLK

DATA

LED0

LED1

128 BYTES

SRAM + STACK

WATCH DOG

TIMER

BASE TIMER

I/O PORTS

RESET

V

GND

6502
CPU

INT. CONTROLLER

DD

POWER-ON RESET/

LOW VOLTAGE RESET

Pin and Pad Descriptions

Pin No. Pad No. Designation I/O Description

1 1 GND P Ground pin
2 2 NC - No connection, recommended to connect VDD or floating
3 3 DATA I/O
4 4 CLK I/O

5 - 9,

11 - 34

10 10

35 - 37 35 - 37 LED0 -

5 - 9,

11 - 34

P30 - P34,

P00 - P27

RESET

I/O Bi-directional I/O pins

O LED direct sink pins

LED2

38 38

VDD

P Power supply

39 39 R/OSCO I

40 40 OSCI - No connection for RC OSC, connected for 4MHz ceramic

I/O, 10KΩ pull-up resistor for communication
I/O, 10KΩ pull-up resistor for communication

I

RESET signal input pin with internal pull up resistor; Active low

47KΩ resistor connected for RC OSC or 4MHz ceramic resonator
connected

resonator

LED2

P00 - P07

P10 - P17

P20 - P27

P30 - P34

* Under the constraint of the maximum frequency variation, (∆F/F)max, ≤ ±1%, code 3 (ceramic resonator option) must be

selected and pin 39 and pin 40 are connected to a ceramic resonator. If (∆F/F)max, ≤ ±10%, code 1 (RC OSC option) is
recommended to be selected and pin39 connects a 47KΩ resistor with, ≤ ±1% accuracy to VDD and pin 40 is floating.

2

Functional Description

6502 CPU

6502 is an 8-bit CPU. Refer to 6502 data sheet for details.

7 0

ACCUMULATOR A

7 0

INDEX REGISTER X

7 0

INDEX REGISTER Y

0000

007F

00C0
00CF

SRAM

UNUSED

SYSTEM REGISTERS

NT6868A

STACK PTR

15 0

PROGRAM COUNTER PC

7 0

S

7 0

S V B D I Z C

STACK POINTER SP

STATUS REGISTER P

CARRY
ZERO
INTERRUPT MASK
DECIMAL MODE
BREAK
OVERFOLW
SIGN

F000

FFFA

FFFB

FFFC

FFFD

FFFE

FFFF

UNUSED

USER ROM

NMI-L

NMI-H

RST-L

RST-H

IRQ-L

IRQ-H

Figure 1. 6502 CPU Registers and Status Flags Figure 2. NT6868A Memory Map

NMI VECTOR

IRQ VECTOR

3

NT6868A

System Reserved Registers

Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

$00C0 BT BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 W
$00C1 TCON - - - - - - -

$00C2 CLRIRQX - - - - - - - CLRIRQTMR W
$00C3 PORT0 PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 RW
$00C4 PORT1 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 RW
$00C5 PORT2 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 RW
$00C6 PORT3 - - - PD34 PD33 PD32 PD31 PD30 RW
$00C7 CLK - - - - - - - CLK RW
$00C8 DATA - - - - - - - DATA RW

$00C9 LED - - - - - LED2 LED1 LED0 W
$00CA CLRWDT 0 1 0 1 0 1 0 1 W
$00CB X X X X X X X X X X
$00CC X X X X X X X X X X
$00CD X X X X X X X X X X
$00CE X X X X X X X X X X

$00CF X X X X X X X X X X

- : no effect X : access not allowed

4K X 8 ROM

The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.

Power-On Reset

Built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the

150ms pulse occurs at 60% of VDD when powered on.

ENBT

128 X 8 SRAM

The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. User can allocate stack area in the
SRAM by setting stack pointer register (S). Because the
6502C default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.

For example :

LDX #$7F
TXS

V

60%

power

DD

The start of 150ms pulse

t

W

4

NT6868A

Timing Generation

This block generates the system timing and control
signal supplied to CPU and on-chip peripherals. There
are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both of them are
mask optional and generate a 4MHz system clock. They
also generates 2MHz for CPU, and 1MHz for base timer.
The following shows the relationship of code type
number and oscillation type.

Oscillator Type Code Number

RC OSC 1
Ceramic Resonator 3

Base Timer

The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing

a '0' to 'ENBT' in the TCON (Timer Control) register. The ENBT is a level trigger.

The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)

External Resistor

(KΩ)

39 4.7
43 4.44
47 4
56 3.68

RC OSC Frequency (MHz)

Base timer structure:

8-Bit timer

1µs

BT pre-load data:

Addr. Bit 7 6 5 4 3 2 1 0

$00C0 BT BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 (W)

Timer Control Regisrer:

$00C1 TCON - - - - - - -

BT7 BT6 BT5 BT4 BT2 BT2 BT1 BT0

ENBT

TMRINT

(W)

INT. Controller

When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER
interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software.

Interrupt Control Register:

Addr. Bit 7 6 5 4 3 2 1 0

$00C2 CLRIRQX - - - - - - - CLRIRQTMR (W)

5

NT6868A

I/O Ports

The NT6868A has 31 pins dedicated to input and output. These pins are grouped into 6 ports, as follows:

PORT 0 (P00 - P07):

Port 0 is an 8-bit bi-directional CMOS I/O port that is internally pulled High by PMOS. Each pin of port 0 can be bit
programmed as an input or output pin under the software control. When programmed as output, data is latched to the port
data register and output to the pin. Port 0 pins with ''1'' written to them are pulled high by the internal PMOS pull-ups, and
are used as inputs in that state. These input signals can then be read. The port output is High after reset.

PORT 1 ( P10 - P17 ) : Functions the same as PORT 0.
PORT 2 ( P20 - P27) : Functions the same as PORT 0.
PORT 3 ( P30 - P34) : Functions the same as PORT 0.

CLK & DATA : These two pins have the same structure as I/O ports, except for the 10KΩ internal pull-ups.

PORT Registers:

Addr. Bit 7 6 5 4 3 2 1 0
$00C3 PORT0 PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 (RW)
$00C4 PORT1 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 (RW)
$00C5 PORT2 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 (RW)
$00C6 PORT3 - - - PD34 PD33 PD32 PD31 PD30 (RW)
$00C7 CLK - - - - - - - CLK (RW)
$00C8 DATA - - - - - - - DATA (RW)

WREN

DB

RST

RDENB

Latch

L

Q

D

SD

IO Port Structure

VDD

Weak PMOS

IO

6

NT6868A

RESET

LED Port

There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.

Addr. Bit 7 6 5 4 3 2 1 0
$00C9 LED - - - - - LED2 LED1 LED0 (W)

WREN

DB

RST

LED [ 0 ]

L

Q

D

SD

WREN

DB

RST

L

Q

D

SD

VDD

LED [ 1:2 ]

LED0 Port Structure LED1, LED2 Port Structures

Watch-Dog Timer

NT6868A implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be
cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.

For example:
LDA #$55
STA $00CA

Addr. Bit 7 6 5 4 3 2 1 0

$00CA CLRWDT 0 1 0 1 0 1 0 1 (W)

Low Voltage Reset (LVR) Circuit

The NT6868A will check on the voltage level of power supply. When the voltage level of power supply is below a threshold
of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage
of 3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about
150ms.

NT6868A can also be externally reset via RESET pin. A reset is initiated when the signal at the RESET pin is held Low
for at least 10 system clock. As soon as RESET signal goes high, the NT6868A begins to be reset for about 150ms. The
following shows the definition of RESET input low pulse width.

V

V

DD

20%V

DD

20%V

Trstb

DD

DD

7

NT6868A

Absolute Maximum Ratings*

DC Supply Voltage . . . . . . . . . . . . . . . . . -0.3V to +7.0V

Input/Output Voltage . . . . . . . .GND -0.2V to VDD + 0.2V

Operating Ambient Temperature . . . . . . . .0°C to +70°C

Storage Temperature . . . . . . . . . . . . . .-55°C to +125°C

Operating Voltage (VDD) . . . . . . .. . . . . . . .+4.5V to 5.5V

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified)

Symbol Parameter Min. Typ. Max. Unit Conditions

ICC
VIH
VIL

VOH1

VOH2
VOL1

Power Supply Current 20 mA No load
Input High Voltage 2 V
Input Low Voltage 0.8 V
Output High Voltage (Port 0, 1, 2,

3)
Output High Voltage (CLK, DATA) 2.4 V

Output Low Voltage (PORT 0, 1, 2) 0.4 V

2.4 V

IOH = -100µA

IOH = -400µA

IOL = 4mA
VOL2
VOL3

∆F/F

∆F/F

ILED

VLVR

TPOR

TRSTB

RPH

Output Low Voltage (PORT 3) 0.4 V
Output Low Voltage (CLK, DATA) 0.4 V
Initial Frequency Variation 1 +/-10 % For RC OSC option

Frequency Variation 2 +/-1 % For ceramic resonator

LED Sink Current (LED 0, 1, 2) 10 14 17 mA
Low Voltage Reset Threshold 3.0 V
Power-on Reset Time 120 150 180 ms

RESET Input Low Pulse Width
RESET Pull High Resistor

2.5
220

µs

KΩ

IOL = 5mA
IOL = 10mA

only; By Lots

option only; By Lots
VOL = 3.2V

10 system clocks

8

NT6868A

Application Circuit For Windows 98 Keyboard (for reference only)

P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30

NT6868A

P31

P20
P21
P22
P23
P24
P25
P26
P27

R0 R1 R2 R3 R4 R5 R6 R7

Pause

Q

W

E

R

U

O

P

Scroll

Lock

K14

7
Home

8

9
PgUp

+

Wake
Up

Kor_L

I

Power Sleep

Lock

F7

A

S

F3

D

T

F

Y

J

}
]

K

L

{

:

[

;

|
\(K29)

1
End

2

3

PgDn
(R)
Enter

(R)
Shift

WINR

Tab

Caps

Back
Space

4

5

6

K107
(L)
Shift

WINL

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

V

V

DD

DD

Esc

(K45)

Macro

F4

G

H

F6

"
'

(L)
Alt

F11

Space
0

Ins

.
Del

4.7 - 10 mf

GND

LED0

LED1

LED2

RESET

DATA

CLK

R/OSCO

|
\(K42)

Enter

Num
Lock

/

Scroll Lock

Num Lock

Caps Lock

0.1m f

V

47K (System clock can be decreased
by increasing the resistance)

Wake

(R)
Ctrl

Z

X

C

V

M

<

,

>

.

*

Up

K131

K132

K133

APP

K56

F12

(L)

Ctrl

~

F1

F2
%

B

5
^

N

6
+

=

F8

?

/

-

(R)

Alt

F9

Delete

Insert

Page

-

Up

Home

V

Optional

KBD DATA

KBD CLOCK

DD

,

DD

F5

@

Print

Screen

F10

Power

Sleep

Page
Down

End

Kor_R

!

1

2
#

3
$

4
&

7

*
8

(
9

)
0

9

Application Circuit For Windows 2000 Standard Code

S0
S1
S2
S3
S4
S5
S6
S7
S8

S9
S10
S11
S12
S13
S14
S15
S16
S17
S18

P15
P30
P31
P00
P01
P02
P03
P04

P13
P14
P12

P10
P07

P06
P05
P11
P16
P17
P32

NT6868A/C

R_OSC

LED 0

LED 1

LED 2

VDD

GND

NT6868A

47K

Scroll Lock

.1uF

Num Lock

Caps Lock

VDD

10uF

GND

R0

R1

R2

R3

R4

R5

R6

R7

P20
P21
P22

P23
P24
P25
P26
P27

DATA

CLOCK

RESET

DATA

CLOCK

10

0.1uF

10

Key Matrix definition for Windows 2000 Standard Code

Pause R-Ctrl L-Ctrl F5

126 64 58 116

Q Tab A Esc Z (K131)

17 16 31 110 46 131 1 2

W

18 30 32 45 47 132 112 3

E

19 114 33 115 48 133 113 4

R

20 21 34 35 49 50 6 5

U

23 22 37 36 52 51 7 8

I

24 28 38 117 53 56 13 9

O

25 118 39 54 162 119 10

P

26 27 40 41 42 55 12 11

Scroll Lock L-Alt R-Alt Print

125 60 62 124

(K14) Back Space |

14 15 29 122 43 123 120 121

7

91 92 93 61 90 84 76 163

(Home)

8

96 97 98 99 95 89 75 164

( )

9

101 102 103 104 100 105 85 86

(Page Up)

+ (K107) Enter

106 107 108 83 79 80 81

(Num)

Wake Up L-Shift R-Shift

165 44 57

Volume -

186

Kor_L

134

R0

Power Sleep

163 164 165

Caps Lock S

F3

T

Y

}
]

F7

D

F

J

K

L

(K45)

F4

G

H

F6

X

C

V

M

<

,

>

.

{
[

:
;

"

'

|
\

F11 Enter F12 F9 F10

(101)

\

4 1

( )

5 2

(Num)

6

( )

(End)

( )

3

(Page Dn)

Space Num Lock Delete Power

0

(Ins)

(Num)

.

(Del)

(Num)

Media

Next

180

Media Stop

WWW
Home

189

WWW

Refresh

193

R4

R1

160

191

195

L-Win

WWW

Forward

Media
Select

WWW Mail

187

R-Win

161

Calculator

196

R2

(Num)

Media

Previous

181

WWW
Search

188

WWW Stop

192

My

Computer

197

R3

Wake Up

!

1

@

(K132)

~

`

F1

2

(K133)

F2

#
3

B

N

(K56)

App

%

5
^

6
+

=

F8

$
4

&

7
*

8

(

9

?

/

_

-

)

0

Screen

/ Insert Sleep

* - Page Up Page Down

(Num)

Home

Media Play Media Mute

183 184 185182

WWW

Bookmark

194

R5

R6

End

Volume +

WWW Back

190

Kor_R

135

R7

NT6868A

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

11

Bonding Diagram

NT6868A

P

P

P

P

P

P

P

P

P

1

1

1

1

1

1

7

6

5

4

1

3

2

1

P

1

0

0

0

7

6

26 25 24 23 22 21 20 19 18 17

27

P20

28

P21

29

P22

30

P23

31

P24

32

P25

33

P26

34

P27

35

LED0

36

LED1

R

V

L

D

/

E

D

O

D

S

2

C
O

*Substrate Connect to V

Pad No. Designation X Y

NT6868AH

Y

(0, 0)

40393837

1

G

O

N

S

D

C

I

1930.4µm

16

P05

15

P04

14

P03

13

P02

12

P01

11

P00

X

NCD

C

A

L

T

K

A

or Keep Floating

DD

10

9

8

7

6 5 4 3 2

P
3
0

1752.6µm

RESET

P34

P33

P32

P31

unit: µm

Pad No. Designation X Y

1 GND -74.4 -712.1
2 NC 55.6 -727.5
3 DATA 185.6 -727.5
4 CLK 445.6 -727.5
5 P30 575.6 -727.5
6 P31 812.9 -728.1
7 P32 818.1 -460.6
8 P33 818.1 -330.6
9 P34 818.1 -200.6

10 RESET 818.1 -70.6
11 P00 818.1 59.4
12 P01 818.1 189.4
13 P02 818.1 319.4
14 P03 818.1 449.4
15 P04 818.1 579.4
16 P05 818.1 721.9
17 P06 426.1 727.5
18 P07 296.1 727.5
19 P10 166.1 727.5
20 P11 36.1 727.5

21 P12 -93.9 727.5
22 P13 -223.9 727.5
23 P14 -353.9 727.5
24 P15 -483.9 727.5
25 P16 -613.9 727.5
26 P17 -756.4 727.5
27 P20 -818.2 519.3
28 P21 -818.2 389.3
29 P22 -818.2 259.3
30 P23 -818.2 129.3
31 P24 -818.2 -0.7
32 P25 -818.2 -130.7
33 P26 -818.2 -260.7
34 P27 -818.2 -390.7
35 LED0 -818.2 -520.7
36 LED1 -818.2 -666.8
37 LED2 -594.4 -661.6

38 VDD -464.4 -661.6
39 R/OSCO -334.4 -661.6
40 OSCI -204.4 -661.6

12

Ordering Information

Part No. Package

NT6868AH CHIP FORM

NT6868A 40L DIP

Code Type No. Oscillation Type

1 Built-in RC OSC
3 Ceramic Resonator

Function Package Type Order Information

Windows 95 keyboard DIP NT6868A-0011

COB NT6868AH-0046

Windows 98 keyboard DIP NT6868A-10100

NT6868A

COB NT6868AH-10088

13

NT6868A

Package Information

DIP 40L Outline Dimensions unit: inches/mm

D

2140

E1

1

S

AL

A2

B

B1

20

A1

Base Plane

Seating Plane

e1

α

E

C

eA

Symbol Dimensions in inches Dimensions in mm

A 0.210 Max. 5.33 Max.
A1 0.010 Min. 0.25 Min.
A2

0.155±0.010 3.94±0.25

B 0.018 +0.004 0.46 +0.10

-0.002 -0.05

B1 0.050 +0.004 1.27 +0.10

-0.002 -0.05

C 0.010 +0.004 0.25 +0.10

-0.002 -0.05

D 2.055 Typ. (2.075 Max.) 52.20 Typ. (52.71 Max.)

E

0.600±0.010 15.24±0.25
E1 0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.)
e1

L

0.100±0.010 2.54±0.25

0.130±0.010 3.30±0.25

α 0° ~ 15° 0° ~ 15°

eA

0.655±0.035 16.64±0.89

S 0.093 Max. 2.36 Max.

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E1 does not include resin fins.

3. Dimension S includes end flash.

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