Datasheet NT5SV64M4AT-7K, NT5SV32M8AT-75B, NT5SV32M8AT-7K, NT5SV16M16AT-75BL, NT5SV16M16AT-7KL Datasheet (NANYA)

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM Features

• High Performance:

3

-7K

CL=2 fCKClock Frequency 133 133 100 MHz tCKClock Cycle 7.5 7.5 10 ns tACClock Access Time tACClock Access Time

1. Terminated load. See AC Characteristics on page 37.

2. Unterminated load. See AC Characteristics on page 37.

3. t

= t

RCD

= 2 CKs

RP

1

— — — ns

2

5.4 5.4 6 ns

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BA0/BA1 (Bank Select)

• Programmable CAS Latency: 2, 3

• Programmable Burst Length: 1, 2, 4, 8

• Programmable Wrap: Sequential or Interleave

-75B, CL=3

-8B,

CL=2

Units

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard Power operation

• 8192 refresh cycles/64ms

• Random Column Address every CK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Package: 54-pin 400 mil TSOP-Type II

• -7K parts for PC133 2-2-2 operation

-75B parts for PC133 3-3-3 operation

-8B parts for PC100 2-2-2 operation

Description

The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 256Mbit single transistor CMOS DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock.

RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device.

cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation.

Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported.

Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A12, BA0, BA1 during a mode register set

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256Mb Synchronous DRAM

Pin Assignments for Planar Components (Top View)

V

DD

DQ0

V

DDQ

DQ1 DQ2

V

SSQ

DQ3 DQ4

V

DDQ

DQ5 DQ6

V

SSQ

DQ7

V

DD

LDQM

WE CAS RAS

CS BA0 BA1

A10/AP

A0 A1

A2 A3

V

DD

V

DD

DQ0

V

DDQ

NC

DQ1

V

SSQ

NC

DQ2

V

DDQ

NC

DQ3

V

SSQ

NC

V

DD

NC

WE CAS RAS

CS BA0 BA1

A10/AP

A0 A1

A2 A3

V

DD

V

DD

NC

V

DDQ

NC

DQ0

V

SSQ

NC NC

V

DDQ

NC

DQ1

V

SSQ

NC

V

DD

NC

WE CAS RAS

CS BA0 BA1

A10/AP

A0 A1

A2 A3

V

DD

1 2 3 4 5 6

7 8 9 10 11 12 13 14 15 16 17 18

19 20 21

22 23

24 25 26 27

54 53 52 51 50 49

48 47 46 45 44 43 42 41 40 39 38 37

36 35 34

33 32

31 30

29 28

V

SS

NC V

SSQ

NC DQ3 V

DDQ

NC NC V

SSQ

NC DQ2 V

DDQ

NC V

SS

NC DQM CK CKE

A12 A11 A9

A8 A7

A6 A5

A4 V

SS

V

SS

DQ7 V

SSQ

NC DQ6 V

DDQ

NC DQ5 V

SSQ

NC DQ4 V

DDQ

NC V

SS

NC DQM CK CKE

A12 A11 A9

A8 A7

A6 A5

A4 V

SS

V

SS

DQ15 V

SSQ

DQ14 DQ13 V

DDQ

DQ12 DQ11 V

SSQ

DQ10 DQ9 V

DDQ

DQ8 V

SS

NC UDQM CK CKE

A12 A11 A9

A8 A7

A6 A5

A4 V

SS

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54-pin Plastic TSOP(II) 400 mil

16Mbit x 4 I/O x 4 Bank

NT5SV64M4AT

8Mbit x 8 I/O x 4 Bank

NT5SV32M8AT

4Mbit x 16 I/O x 4 Bank

NT5SV16M16AT

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256Mb Synchronous DRAM

Pin Description

CK Clock Input DQ0-DQ15 Data Input/Output

CKE (CKE0, CKE1) Clock Enable DQM, LDQM, UDQM Data Mask

CS Chip Select V RAS Row Address Strobe V CAS Column Address Strobe V

WE Write Enable V

BA1, BA0 Bank Select NC No Connection

A0 - A12 Address Inputs — —

DD

SS

DDQ

SSQ

Power for DQs (+3.3V)

Input/Output Functional Description

Symbol Type Polarity Function

CK Input

CKE, CKE0,

CKE1

CS Input Active Low

RAS, CAS, WE Input Active Low

BA1, BA0 Input — Selects which bank is to be active.

A0 - A12 Input —

DQ0 - DQ15

DQM

LDQM

UDQM

VDD, V

SS

V

DDQ VSSQ

Input Active High

Input-

Output

Input Active High

Supply — Power and ground for the input buffers and the core logic. Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity.

Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.

CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11), when sampled at the rising clock edge. Assume the x4 organization.

A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BA0 and BA1 are used to define which bank to precharge.

— Data Input/Output pins operate in the same manner as on conventional DRAMs.

The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high.

Power (+3.3V)

Ground

Ground for DQs

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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Ordering Information

Organization Part Number

NT5SV64M4AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

64M x 4

32M x 8

16M x 16

SP : Standard Power ; LP : Low power

NT5SV64M4AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV64M4AT-8B 125MHz@CL3 100MHz@CL2 PC100 NT5SV32M8AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

NT5SV32M8AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV32M8AT-8B 125MHz@CL3 100MHz@CL2 PC100

NT5SV16M16AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

NT5SV16M16AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV16M16AT-8B 125MHz@CL3 100MHz@CL2 PC100

NT5SV16M16AT-7KL 143MHz@CL3 133MHz@CL2 PC133 , PC100

NT5SV16M16AT-8BL 125MHz@CL3 100MHz@CL2 PC100

Speed Grade

Clock Frequency@CAS Latency Note

Package

400mil 54-

TSOP II

Self

Refresh

SP

LPNT5SV16M16AT-75BL 133MHz@CL3 100MHz@CL2 PC133 , PC100

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256Mb Synchronous DRAM

Block Diagram

CK

A11

A12 BA1 BA0 A10

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

CKE Buffer

CK Buffer

Address Buffers (15)

Counter

Refresh

Column

Column Decoder

Cell Array

Memory Bank 0

Row Decoder

Sense Amplifiers

Generator

Control Signal

Mode Register

Counter

Address

Row Decoder

Column Decoder

Sense Amplifiers

Data Control Circuitry

Cell Array

Memory Bank 1

DQM

DQ

0

DQ

X

Data Input/Output Buffers

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Column Decoder

Memory Bank 3

Sense Amplifiers

CS RAS CAS

WE

Column Decoder

Cell Array

Memory Bank 2

Row Decoder

Command Decoder

Sense Amplifiers

Row Decoder

Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15).

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Cell Array

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power On and Initialization

The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs.

Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and V state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.

pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP”

DDQ

Programming the Mode Register

For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued.

After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t

CAS Latency

The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section.

has elapsed.

RSC

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256Mb Synchronous DRAM

Mode Register Operation (Address Input For Mode Set)

BA0BA1

A12

A11 A3A4 A2 A1 A0A10 A9 A8 A7 A6 A5

Operation Mode

M14 M13 M12 M11 M10 M9 M8 M7 Mode

0 0 0 0 0 0 0 0 Normal

0 0 0 0 0 1 0 0

Multiple Burst

with

Single Write

CAS Latency

M6 M5 M4 Latency

0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

BT Burst LengthCAS Latency

Burst Type

M3 Type

0 Sequential 1 Interleave

Address

Bus (Ax)

Mode

Register(Mx)

Burst Length

Length

M2 M1 M0

Sequential Interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved

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256Mb Synchronous DRAM

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A12, BA0, and BA1.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below.

The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organization: x4, x8, or x16).

Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected.

Burst Length and Sequence

Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)

2

4

8

x x 0 0, 1 0, 1

x x 1 1, 0 1, 0 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

Note: Page length is a function of I/O organization and column addressing.

x4 organization (CA0-CA9, CA11); Page Length = 2048 bits x8 organization (CA0-CA9); Page Length = 1024 bits x16 organization (CA0-CA8); Page Length = 512 bits

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256Mb Synchronous DRAM

Bank Activate Command

In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in the selected bank.

The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (t

). Once a bank has been activated it must be precharged before another Bank Activate command can be

RCD

applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t is specified as t

RAS(max)

.

). The maximum time that each bank can be held active

RRD

Bank Activate Command Cycle

(CAS Latency = 3, t

RCD

= 3)

T0 T2T1 T3 Tn Tn+1 Tn+2 Tn+3

CK

ADDRESS

COMMAND

: “H” or “L”

Bank A

Row Addr.

Bank A

Activate

Bank A

Col. Addr.

RAS-CAS delay (t

NOP NOP NOP NOP

RCD

)

Write A

with Auto

Precharge

. . . . . . . . . .

RAS Cycle time (tRC)

Bank B

Row Addr.

RAS - RAS delay time (t

Bank B

Activate

Bank A

Row Addr.

)

RRD

Bank A

Activate

Bank Select

The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation.

Bank Selection Bits

BA0 BA1 Bank

0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3

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256Mb Synchronous DRAM

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (t whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.

The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register.

Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (t

) is what limits the number of random column accesses to an activated bank.

REF

A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address.

Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle.

). WE must also be defined at this time to determine

RCD

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256Mb Synchronous DRAM

Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register.

Burst Read Operation

(Burst Length = 4, CAS latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

READ A NOP NOP NOP NOP NOP NOP NOP

DOUT A

0

DOUT A

NOP

DOUT A2DOUT A

1

DOUT A1DOUT A

0

3

DOUT A

2

3

Read Interrupted by a Read

A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears.

Read Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

CK

COMMAND

CAS latency = 2

t

CK2

CAS latency = 3

t

CK3

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DQs

,

DQs

,

T0 T2T1 T3 T4 T5 T6 T7 T8

READ A READ B NOP NOP NOP NOP NOP NOP

DOUT A

DOUT B

0

DOUT A

NOP

DOUT B1DOUT B

0

DOUT B

0

DOUT B1DOUT B

0

DOUT B

2

3

DOUT B

2

3

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256Mb Synchronous DRAM

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus.

Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

CK

DQM

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

: “H” or “L”

T0 T2T1 T3 T4 T5 T6 T7 T8

DQM high for CAS latency = 2 only. Required to mask first bit of READ data.

DIN A

NOPNOP READ A WRITE A NOP NOP NOP

DIN A

0

DIN A

0

DIN A

1

DIN A

1

DIN A

2

DIN A

3

NOP NOP

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256Mb Synchronous DRAM

Non-Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

DQM

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

: DQM high for CAS latency = 2 : DQM high for CAS latency = 3

DIN A

NOPNOPREAD A WRITE A NOP NOP NOP

CL = 2: DQM needed to mask first, second bit of READ data.

DIN A

0

CL = 3: DQM needed to mask first bit of READ data.

DIN A

0

DIN A

1

DIN A

1

DIN A

2

DIN A

3

NOP NOP

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256Mb Synchronous DRAM

Burst Write Command

The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.

Burst Write Operation

(Burst Length = 4, CAS latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

DQs

: “H” or “L”

NOP

are registered on the same clock edge.

WRITE A NOP NOP NOP NOP NOP NOP

DIN A

0

DIN A

1

NOP

DIN A

2

3

Extra data is masked.The first data element and the Write

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Write

CK

COMMAND

DQs

REV 1.0

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(Burst Length = 4, CAS latency = 2, 3)

T0 T2T1 T3 T4 T5 T6 T7 T8

NOP WRITE A WRITE B NOP NOP NOP NOP NOP

1 CK Interval

DIN A

DIN B

0

DIN B

0

NOP

DIN B

1

DIN B

2

3

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Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory.

Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

CK

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

: “H” or “L”

T0 T2T1 T3 T4 T5 T6 T7 T8

NOPWRITE A READ B NOP NOP NOP NOP NOP NOP

DIN A

0

Input data for the Write is masked.

DOUT B

DOUT B1DOUT B

0

DOUT B

2

DOUT B1DOUT B

0

Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid

data contention.

3

DOUT B

2

3

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Non-Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

CK

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

: “H” or “L”

T0 T2T1 T3 T4 T5 T6 T7 T8

WRITE A READ B NOP NOP NOP NOP NOP NOP

DIN A

NOP

DIN A

0

1

DIN A

1

Input data for the Write is masked.

DOUT B0DOUT B

DOUT B

Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid

data contention.

DOUT B2DOUT B

1

DOUT B

0

DOUT B2DOUT B

1

3

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Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands.

A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied.

When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t

RAS(min)

. If this interval does not satisfy t

RAS(min)

then t

must be extended.

RCD

Burst Read with Auto-Precharge

CK

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

T0 T2T1 T3 T4 T5 T6 T7 T8

READ A

Auto-Precharge

Begin Auto-precharge

NOP NOPNOP

t

‡

RP

DOUT A

(Burst Length = 1, CAS Latency = 2, 3)

NOP

NOP NOP NOP NOP

*

0

t

‡

RP

DOUT A

*

0

Bank can be reactivated at completion of tRP.

*

‡ t

is a function of clock cycle time and speed sort.

RP

See the Clock Frequency and Latency table.

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Burst Read with Auto-Precharge

(Burst Length = 2, CAS Latency = 2, 3)

CK

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

T0 T2T1 T3 T4 T5 T6 T7 T8

READ A

Auto-Precharge

Begin Auto-precharge

NOP NOP

NOP

DOUT A

Burst Read with Auto-Precharge

RP

NOP NOP NOP NOP

*

1

‡

DOUT A

0

*

1

Bank can be reactivated at completion of tRP.

*

‡ t

is a function of clock cycle time and speed sort.

RP

See the Clock Frequency and Latency table.

NOP

t

‡

RP

DOUT A

0

t

DOUT A

(Burst Length = 4, CAS Latency = 2, 3)

CK

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

T0 T2T1 T3 T4 T5 T6 T7 T8

READ A

Auto-Precharge

NOP

DOUT A

0

Begin Auto-precharge

NOP

DOUT A1DOUT A

DOUT A

NOP NOP NOP NOP

t

‡

RP

DOUT A

2

DOUT A

0

DOUT A

1

Bank can be reactivated at completion of tRP.

*

‡ t

RP

See the Clock Frequency and Latency table.

*

3

t

‡

RP

DOUT A

2

is a function of clock cycle time and speed sort.

NOPNOP

*

3

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Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.

Burst Read with Auto-Precharge Interrupted by Read

(Burst Length = 4, CAS Latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

CAS latency = 2

t

DQs

CK2,

CAS latency = 3

t

DQs

,

CK3

READ A

Auto-Precharge

NOP

READ B

DOUT A

NOP

t

‡

RP

DOUT A1DOUT B

0

t

DOUT A

NOP NOP NOP NOP

*

DOUT B

0

‡

RP

DOUT A

0

Bank can be reactivated at completion of tRP.

*

‡ t

is a function of clock cycle time and speed sort.

RP

See the Clock Frequency and Latency table.

*

DOUT B

1

DOUT B2DOUT B

1

DOUT B

0

DOUT B2DOUT B

1

NOP

3

If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.

Burst Read with Auto-Precharge Interrupted by Write

(Burst Length = 8, CAS Latency = 2)

CK

COMMAND

T0 T2T1 T3 T4 T5 T6 T7 T8

READ A

Auto-Precharge

NOP

WRITE B

NOP NOP NOP

NOP

CAS latency = 2

t

CK2,

DQM

REV 1.0

May, 2001

DQs

DOUT A

t

‡

RP

0

D IN B

Bank can be reactivated at completion of tRP.

*

‡ t

is a function of clock cycle time and speed sort..

RP

See the Clock Frequency and Latency table .

DIN B

0

*

D IN B

1

D IN B

2

D IN B

3

4

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If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing autoprecharge cannot be reactivated until t

, Data-in to Active delay, is satisfied.

DAL

Burst Write with Auto-Precharge

(Burst Length = 2, CAS Latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

WRITE A

Auto-Precharge

DIN A

NOP NOP NOP NOP

t

‡

DAL

DIN A

0

DIN A

1

t

‡

DAL

1

*

NOP

Bank can be reactivated at completion of t

*

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

NOP NOPNOP

*

DAL

.

Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until t

is satisfied.

DAL

Burst Write with Auto-Precharge Interrupted by Write

(Burst Length = 4, CAS Latency = 3)

T0 T1 T2 T3 T4 T5

CK

T6 T7 T8

COMMAND

CAS latency = 3

t

CK3,

REV 1.0

May, 2001

DQs

WRITE A

Auto-Precharge

DIN A

NOP NOP NOP

DIN A

0

1

WRITE B

DIN B

t

‡

DAL

DIN B

0

NOP

DIN B

1

20

NOP NOPNOP

*

DIN B

2

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3

Bank can be reactivated at completion of t

*

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

DAL

.

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256Mb Synchronous DRAM

Burst Write with Auto-Precharge Interrupted by Read

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

(Burst Length = 4, CAS Latency = 3)

COMMAND

CAS latency = 3

t

DQs

,

CK3

WRITE A

Auto-Precharge

DIN A

0

NOP

DIN A

READ B

DIN A

1

2

NOP NOP NOP

NOP

t

‡

DAL

DOUT B

Bank A can be reactivated at completion of t

*

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

NOPNOP

*

DOUT B1DOUT B

0

DAL

2

.

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued.

Bank Selection for Precharge by Address Bits

A10 Bank Select Precharged Bank(s)

LOW BA0, BA1 Single bank defined by BA0, BA1

HIGH DON’T CARE All Banks

For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as t

After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).

, Data-in to Precharge delay.

DPL

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Burst Read Followed by the Precharge Command

T0 T2T1 T3 T4 T5 T6 T7 T8

CK

(Burst Length = 4, CAS Latency = 3)

COMMAND

CAS latency = 3

t

DQs

,

CK2

READ Ax

NOP NOP NOP NOP NOP NOP NOP

0

DOUT Ax0DOUT Ax1DOUT Ax2DOUT Ax

Burst Write Followed by the Precharge Command

CK

COMMAND

CAS latency = 2

t

DQs

CK2,

T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

Activate Bank Ax

NOP

WRITE Ax

DIN Ax

NOP NOP NOP

0

DIN Ax

0

Precharge A

1

t

RP

Bank A can be reactivated at completion of tRP.

*

‡ t

is a function of clock cycle and speed sort.

RP

‡

*

3

(Burst Length = 2, CAS Latency = 2)

Precharge A

t

DPL

‡

t

‡

RP

*

REV 1.0

May, 2001

Bank can be reactivated at completion of tRP.

*

‡ t

and tRP are functions of clock cycle and speed sort.

DPL

See the Clock Frequency and Latency table.

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256Mb Synchronous DRAM Precharge Termination

The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency.

Burst Read Interrupted by Precharge

(Burst Length = 8, CAS Latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

READ Ax

NOP NOP NOP NOP NOP NOP NOP

0

DOUT Ax

DOUT Ax1DOUT Ax2DOUT Ax

0

DOUT Ax

Precharge A

t

‡

RP

3

t

‡

RP

DOUT Ax1DOUT Ax2DOUT Ax

0

Bank A can be reactivated at completion of tRP.

‡ t

is a function of clock cycle time and speed sort.

*

RP

See the Clock Frequency and Latency table.

*

3

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Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, t

DPL

.

Precharge Termination of a Burst Write

(Burst Length = 8, CAS Latency = 2, 3)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND

DQM

CAS latency = 2

t

DQs

,

CK2

CAS latency = 3

t

DQs

,

CK3

NOP

WRITE Ax

DIN Ax

NOP NOP

0

DIN Ax

0

DIN Ax

0

‡ t

NOP NOP NOP

t

DPL

DIN Ax

1

is an asynchronous timing and may be completed in one or two clock cycles

DPL

depending on clock cycle time.

DIN Ax

2

t

DPL

2

Precharge A

‡

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Automatic Refresh Command ( CAS before RAS Refresh)

When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC).

Self Refresh Command

The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (t

SREX

).

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Power Down Mode

In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (t

) of the device.

REF

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge.

Power Down Mode Exit Timing

Tm Tm+2Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8

CK

CKE

COMMAND

: “H” or “L”

t

CK

t

CES(min)

NOP COMMAND NOP NOP NOP NOP NOP

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Data Mask

The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency.

Data Mask Activated during a Read Cycle

(Burst Length = 4, CAS Latency = 2)

CK

DQM

COMMAND

DQs

: “H” or “L”

T0 T2T1 T3 T4 T5 T6 T7 T8

NOP READ A NOP NOP NOP NOP NOP NOP NOP

DOUT A

0

1

A two-clock delay before

the DQs become Hi-Z

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.

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Clock Suspend Mode

During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.

When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.

Clock Suspend during a Read Cycle

(Burst Length = 4, CAS Latency = 2)

CK

T0 T2T1 T3 T4 T5 T6 T7 T8

CKE

COMMAND

DQs

: “H” or “L”

A one clock delay before

suspend operation starts

NOP READ A NOP NOP NOP NOP

DOUT A

0

DOUT element at the DQs when the

suspend operation starts is held valid

DOUT A

A one clock delay to exit

the Suspend command

1

DOUT A

2

If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited.

Clock Suspend during a Write Cycle

(Burst Length = 4, CAS Latency = 2)

CK

CKE

COMMAND

T0 T2T1 T3 T4 T5 T6 T7 T8

A one clock delay to exit

A one clock delay before

suspend operation starts

NOP WRITE A NOP NOP NOP NOP

the Suspend command

DQs

: “H” or “L”

REV 1.0

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DIN A

0

DIN A

1

2

DIN is masked during the Clock Suspend Period

DIN A

3

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Command Truth Table (See note 1)

CKE

Function Device State

Mode Register Set Idle H X L L L L X OP Code Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L L L L H X X X X

Exit Self Refresh

Single Bank Precharge

Precharge all Banks

Bank Activate Idle H X L L H H X BS Row Address 2 Write Active H X L H L L X BS L Column 2 Write with Auto-Precharge Active H X L H L L X BS H Column 2 Read Active H X L H L H X BS L Column 2 Read with Auto-Precharge Active H X L H L H X BS H Column 2 Reserved H X L H H L X X X X No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X

Power Down Mode Entry Idle/Active H L

Power Down Mode Exit

Idle (SelfRefresh)

See Current State Table

Any (Power Down)

Current

Cycle

L H

H X L L H L X BS L X 2

H X L L H L X X H X

L H

CS RAS CAS WE DQM

H X X X

L H H H

H X X X

L H H H

H X X X

L H H H

BA0,

X X X X

X X X X 6, 7

BA1

A10

A12, A11,

A9-A0

Notes

4

5

1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table.

2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3.

3. Not applicable.

4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit.

5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).

6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the devic e state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this mode longer than the Refresh period (t

7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.

REV 1.0

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) of the device. One clock delay is required for mode entry and exit.

REF

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256Mb Synchronous DRAM

Clock Enable (CKE) Truth Table

CKE Command

Current State

Self Refresh

Power Down

All Banks Idle

Any State other than

listed above

H X X X X X X X INVALID 1

L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh

H X X X X X X X INVALID 1

L H H X X X X X Power Down mode exit, all banks idle 2 L H L X X X X X ILLEGAL 2

L L X X X X X X Maintain Power Down Mode H H H X X X H H L H X X 3 H H L L H X 3 H H L L L H X X CBR Refresh H H L L L L OP Code Mode Register Set 4 H L H X X X H L L H X X 3 H L L L H X 3 H L L L L H X X Entry Self Refresh 4 H L L L L L OP Code Mode Register Set

L X X X X X X X Power Down 4

H H X X X X X X

H L X X X X X X Begin Clock Suspend next cycle 5

L H X X X X X X Exit Clock Suspend next cycle

L L X X X X X X Maintain Clock Suspend

Current

Cycle

CS RAS CAS WE

BA0,

BA1

A12 - A0

Action Notes

3

Refer to the Idle State section of the Current State Truth Table

3

Refer to the Idle State section of the Current State Truth Table

Refer to operations in the Current State Truth Table

1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t

) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising

CES

clock after CKE goes high (see page 26).

3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.

4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.

5. Must be a legal command as defined in the Current State Truth Table.

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256Mb Synchronous DRAM

Current State Truth Table (Part 1 of 3)(See note 1)

Current State

Idle

Row Active

Read

Write

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

7. The RAS to CAS Delay (t

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

CS RAS CAS WE BA0,BA1 A12 - A0 Description

L L L L OP Code Mode Register Set Set the Mode Register 2 L L L H X X Auto or Self Refresh Start Auto or Self Refresh 2, 3 L L H L BS X Precharge No Operation L L H H BS Row Address Bank Activate Activate the specified bank and row L H L L BS Column Write w/o Precharge ILLEGAL 4 L H L H BS Column Read w/o Precharge ILLEGAL 4 L H H H X X No Operation No Operation

H X X X X X Device Deselect No Operation or Power Down 5

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Precharge 6 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8 L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8 L H H H X X No Operation No Operation

H X X X X X Device Deselect No Operation

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Terminate Burst; Start the Precharge L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Terminate Burst; Start the Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start a new Read cycle 8, 9 L H H H X X No Operation Continue the Burst

H X X X X X Device Deselect Continue the Burst

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Terminate Burst; Start the Precharge L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Terminate Burst; Start a new Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start the Read cycle 8, 9 L H H H X X No Operation Continue the Burst

H X X X X X Device Deselect Continue the Burst

) must occur before the command is given.

RCD

Command

) must be satisfied.

RAS

) is not satisfied.

RRD

Action Notes

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Current State Truth Table (Part 2 of 3)(See note 1)

Current State

Read with

Auto Pre-

charge

Write with Auto

Precharge

Precharging

Row

Activating

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

7. The RAS to CAS Delay (t

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

CS RAS CAS WE BA0,BA1 A12 - A0 Description

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst

H X X X X X Device Deselect Continue the Burst

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst

H X X X X X Device Deselect Continue the Burst

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge No Operation; Bank(s) idle after t L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation No Operation; Bank(s) idle after t

H X X X X X Device Deselect No Operation; Bank(s) idle after t

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4, 10 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation No Operation; Row Active after t

H X X X X X Device Deselect No Operation; Row Active after t

) must occur before the command is given.

RCD

Command

) must be satisfied.

RAS

) is not satisfied.

RRD

Action Notes

RP

RP RP

RCD RCD

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256Mb Synchronous DRAM

Current State Truth Table (Part 3 of 3)(See note 1)

Current State

Write

Recovering

Write

Recovering

with

Auto Pre-

charge

Refreshing

Mode

Register

Accessing

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

7. The RAS to CAS Delay (t

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

CS RAS CAS WE BA0,BA1 A12 - A0 Description

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 9 L H L H BS Column Read Start Read; Determine if Auto Precharge 9 L H H H X X No Operation No Operation; Row Active after t

H X X X X X Device Deselect No Operation; Row Active after t

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4, 9 L H L H BS Column Read ILLEGAL 4, 9 L H H H X X No Operation No Operation; Precharge after t

H X X X X X Device Deselect No Operation; Precharge after t

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL L L H H BS Row Address Bank Activate ILLEGAL L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after t

H X X X X X Device Deselect No Operation; Idle after t

L L L L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL L L H H BS Row Address Bank Activate ILLEGAL L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles

H X X X X X Device Deselect No Operation; Idle after two clock cycles

) must occur before the command is given.

RCD

Command

) must be satisfied.

RAS

) is not satisfied.

RRD

Action Notes

DPL DPL

RC RC

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256Mb Synchronous DRAM

Absolute Maximum Ratings

Symbol Parameter Rating Units Notes

V

DD

V

DDQ

V

IN

V

OUT

T

STG

P

I

OUT

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to VDD+0.3 V 1 Output Voltage -0.3 to VDD+0.3 V 1 Operating Temperature (ambient) 0 to +70 °C 1

A

Storage Temperature -55 to +125 °C 1 Power Dissipation 1.0 W 1

D

Short Circuit Output Current 50 mA 1

Recommended DC Operating Conditions (T

Symbol Parameter

V

DD

V

DDQ

V

IH

V

IL

1. All voltages referenced to VSS and V

2. VIH (max) = VDD + 1.2V for pulse width ≤ 5ns.

3. VIL (min) = VSS - 1.2V for pulse width ≤ 5ns.

Capacitance (T

Symbol Parameter Min. Typ Max. Units Notes

C

I

C

O

Supply Voltage 3.0 3.3 3.6 V 1 Supply Voltage for Output 3.0 3.3 3.6 V 1 Input High Voltage 2.0 — VDD + 0.3 V 1, 2 Input Low Voltage -0.3 — 0.8 V 1, 3

.

SSQ

= 25°C, f = 1MHz, VDD = 3.3V ± 0.3V)

A

Input Capacitance (A0-A12, BA0, BA1, CS, RAS, CAS , WE, CKE, DQM) 2.5 3.0 3.8 pF Input Capacitance (CK) 2.5 2.8 3.5 pF Output Capacitance (DQ0 - DQ15) 4.0 4.5 6.5 pF

Min. Typ. Max.

= 0°C to 70°C)

A

Rating

Units Notes

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256Mb Synchronous DRAM

DC Electrical Characteristics (T

Symbol Parameter Min. Max. Units Notes

I

O(L)

V

I(L)

OH

OL

Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V

Output Leakage Current (D

is disabled, 0.0V ≤ V

OUT

Output Level (LVTTL) Output “H” Level Voltage (

Output Level (LVTTL) Output “L” Level Voltage (I

= 0 to +70°C, VDD = 3.3V ±0.3V)

A

≤ V

DDQ

)

OUT

= -2.0mA)

IOUT

= +2.0mA)

OUT

-1 +1 µA 1

-1 +1 µA

2.4 — V

— 0.4 V

DC Output Load Circuit

3.3 V

1200Ω

Output

50pF

870Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

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256Mb Synchronous DRAM

Operating, Standby, and Refresh Currents (T

Parameter Symbol Test Condition

1 bank operation

Operating Current I

Precharge Standby Current in Power Down Mode

Precharge Standby Current in Non-Power Down Mode

No Operating Current (Active state: 4 bank)

Operating Current (Burst Mode)

Auto (CBR) Refresh Current I

Self Refresh Current I

I

CC2PS

I

CC2NS

I

tRC = tRC(min), tCK = min

CC1

Active-Precharge command cycling without burst operation

CKE ≤ VIL(max), tCK = min,

CC2P

CS = VIH(min) CKE ≤ VIL(max), tCK = Infinity,

CS = VIH(min) CKE ≥ VIH(min), tCK = min,

CC2N

CS = V CKE ≥ VIH(min), tCK = Infinity, 8 8 8 mA 1, 7 CKE ≥ VIH(min), tCK = min,

CC3N

CS = V CKE ≤ VIL(max), tCK = min, 6 6 6 mA 1, 6

CC3P

tCK = min, Read/ Write command cycling,

I

CC4

Multiple banks active, gapless data, BL = 4

tCK = min, tRC = tRC(min)

CC5

CBR command cycling

CC6

(min)

IH

(min)

IH

CKE ≤ 0.2V

= 0 to +70°C, VDD = 3.3V ±0.3V)

A

Speed

-7K -75 B -8B

130 120 115 mA 1, 2, 3

2 2 2 mA 1

30 30 20 mA 1, 5

60 60 45 mA 1, 5

120 120 90 mA 1, 3, 4

175 175 155 mA 1

SP 3 3 3 mA 1,8 LP 1.2 1.2 1.2 mA 8

Units Notes

1. Currents given are valid for a single device. .

2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min).

3. The specified values are obtained with the output open.

4. Input signals are changed once during tCK(min).

5. Input signals are changed once during three clock cycles.

6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).

7. Input signals are stable.

8. SP : Standard power ; LP : Lower power

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256Mb Synchronous DRAM

AC Characteristics (T

= 0 to +70°C, VDD = 3.3V ± 0.3V)

A

1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between VIH and VIL (or between VIL and VIH)

3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point

5. Load Circuit A: AC measurements assume tT = 1.0ns.

6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point

7. Load Circuit B: AC measurements assume tT = 1.2ns.

.

AC Characteristics Diagrams

t

Clock

Input

Output

t

SETUP

t

HOLD

T

V

IH

t

CKL

1.4V

t

AC

t

LZ

t

CKH

t

OH

1.4V

V

IL

Output

Zo = 50Ω

AC Output Load Circuit (A)

Output

Zo = 50Ω

AC Output Load Circuit (B)

Vtt = 1.4V

50Ω

50pF

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Clock and Clock Enable Parameters

Symbol Parameter

t t

t

AC3 (A)

t

AC2 (A)

t

AC3 (B)

t

AC2 (B)

t

t t t

CK3 CK2

CKH

CKL CES CEH

t

SB

t

T

Clock Cycle Time, CAS Latency = 3 7 1000 7.5 1000 8 1000 ns Clock Cycle Time, CAS Latency = 2 7.5 1000 10 — 10 1000 ns Clock Access Time, CAS Latency = 3 — — — — — — ns 1 Clock Access Time, CAS Latency = 2 — — — — — — ns 1 Clock Access Time, CAS Latency = 3 — 5.4 — 5.4 — 6 ns 2 Clock Access Time, CAS Latency = 2 — 5.4 — 6 — 6 ns 2 Clock High Pulse Width 2.5 — 2.5 — 3 — ns Clock Low Pulse Width 2.5 — 2.5 — 3 — ns Clock Enable Set-up Time 1.5 — 1.5 — 2 — ns Clock Enable Hold Time 0.8 — 0.8 — 1 — ns Power down mode Entry Time 0 7.5 0 7.5 0 10 ns Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns

1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.

2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

Units Notes

Common Parameters

Symbol Parameter

t

Command Setup Time 1.5 — 1.5 — 2 — ns

CS

t

Command Hold Time 0.8 — 0.8 — 1 — ns

CH

t

Address and Bank Select Set-up Time 1.5 — 1.5 — 2 — ns

AS

t

Address and Bank Select Hold Time 0.8 — 0.8 — 1 — ns

AH

t

t t

RCD

t

RC

RAS

t

RP

RRD

CCD

RAS to CAS Delay 15 — 20 — 20 — ns 1 Bank Cycle Time 60 — 67.5 — 70 — ns 1 Active Command Period 45 100K 45 100K 50 100K ns 1 Precharge Time 15 — 20 — 20 — ns 1 Bank to Bank Delay Time 15 — 15 — 20 — ns 1 CAS to CAS Delay Time 1 — 1 — 1 — CK

1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

Mode Register Set Cycle

Symbol Parameter

t

RSC

Mode Register Set Cycle Time 15 — 15 — 20 — ns

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

Units Notes

Units

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256Mb Synchronous DRAM

Read Cycle

Symbol Parameter

t

t t t

t

1. AC Output Load Circuit A.

2. AC Output Load Circuit B.

3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).

OH

LZ

HZ3

HZ2

DQZ

Data Out Hold Time

Data Out to Low Impedance Time 0 — 0 — 0 — ns Data Out to High Impedance Time 3 5.4 3 5.4 3 6 ns 3 Data Out to High Impedance Time 3 5.4 3 6 3 6 ns 3 DQM Data Out Disable Latency 2 — 2 — 2 — CK

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

— — — — 2.5 — ns 1

2.7 — 2.7 — 3 — ns 2, 4

Refresh Cycle

Symbol Parameter

t

SREX

1. 8192 a uto refresh cycles.

Refresh Period — 64 — 64 — 64 ms 1

REF

Self Refresh Exit Time 10 — 10 — 10 — ns

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

Units Notes

Write Cycle

Symbol Parameter

t

DAL3

t

DAL2

t

DQW

DS

t

DH

DPL

Data In Set-up Time 1.5 — 1.5 — 2 — ns Data In Hold Time 0.8 — 0.8 — 1 — ns Data input to Precharge 15 — 15 — 20 — ns Data In to Active Delay

CAS Latency = 3 Data In to Active Delay

CAS Latency = 2 DQM Write Mask Latency 0 — 0 — 0 — CK

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

5 — 5 — 5 — CK

Units

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256Mb Synchronous DRAM

Clock Frequency and Latency

Symbol Parameter -7K -75B -8B Units

f

Clock Frequency 143 133 133 100 125 100 MHz

CK

t t t

t

t t t t

t t

t

DQW

t

CK

AA

RP

RCD

RC

RAS

DPL

DAL

RRD

CCD

WL

DQZ

CSL

Clock Cycle Time 7 7.5 7.5 10 8 10 ns CAS Latency 3 2 3 2 3 2 CK Precharge Time 3 2 3 2 3 2 CK RAS to CAS Delay 3 2 3 2 3 2 CK Bank Cycle Time 9 8 9 7 9 7 CK Minimum Bank Active Time 6 6 6 5 6 5 CK Data In to Precharge 2 2 2 2 2 2 CK Data In to Active/Refresh 5 5 5 5 5 5 CK Bank to Bank Delay Time 2 2 2 2 2 2 CK CAS to CAS Delay Time 1 1 1 1 1 1 CK Write Latency 0 0 0 0 0 0 CK DQM Write Mask Latency 0 0 0 0 0 0 CK DQM Data Disable Latency 2 2 2 2 2 2 CK Clock Suspend Latency 1 1 1 1 1 1 CK

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Timing Diagrams Page

AC Parameters for Write Timing..................................................................................................................................42

AC Parameters for Read Timing (3/3/3), BL=4 ...........................................................................................................43

AC Parameters for Read Timing (2/2/2), BL=2 ...........................................................................................................44

AC Parameters for Read Timing (3/2/2), BL=2 ...........................................................................................................45

AC Parameters for Read Timing (3/3/3), BL=2 ...........................................................................................................46

Mode Register Set.......................................................................................................................................................47

Power on Sequence and Auto Refresh (CBR) ............................................................................................................48

Clock Suspension / DQM During Burst Read .............................................................................................................49

Clock Suspension / DQM During Burst Write ............................................................................................................50

Power Down Mode and Clock Suspend......................................................................................................................51

Auto Refresh (CBR).....................................................................................................................................................52

Self Refresh (Entry and Exit).......................................................................................................................................53

Random Row Read (Interleaving Banks) with Precharge, BL=8.................................................................................54

Random Row Read (Interleaving Banks) with Auto-precharge, BL=8 ........................................................................55

Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8........................................................................56

Random Row Write (Interleaving Banks) with Precharge, BL=8 .................................................................................57

Read/Write Cycle ...............................................................................................................................................58

Interleaved Column Read Cycle..................................................................................................................................59

Auto Precharge after a Read Burst, BL=4...................................................................................................................60

Auto Precharge after a Write Burst, BL=4...................................................................................................................61

Burst Read and Single Write Operation......................................................................................................................62

CS Function (Only CS signal needs to be asserted at minimum rate)........................................................................63

REV 1.0

May, 2001

41

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Write Timing

\

RBy

C E H

t

RAz

T16 T17 T18 T 19T15 T22T20 T21

(Burst length = 4, CAS latency = 2)

T13 T14

T 12

T11

T10

RAy

RBy

RR D

t

RAz

RP

t

‡

D PL

t

DH

t

DS

t

‡

DAL

t

Bank 1

Activate

Command

Bank 0

Activate

Command

Bank 0

Precharge

Command

Write

Bank 0

Command

depend on clock cycle time and

DAL

Bank 0

Activate

Command

and t

DPL

t

speed sort. S ee the Clock Frequency and

Latency Table.

‡

CBx CAyRAy

R C

RBx

CK2

t

T2 T3 T4

T 1 T6 T 7 T8 T9T 5

T0

t

CK

C H

t

CS

t

C KL

t

CES

t

CKH

CS

CKE

RAS

CAS

WE

AH

t

RAx

* BA1

A10

RBxCAx

RAx

AS

t

A0-A9,

A11,A12

t

Ax0 Ax3Ax2Ax1 Bx0 Bx3Bx2Bx1 Ay0 Ay3Ay2Ay1

R CD

t

Hi-Z

DQM

DQ

Bank 1

Write with

Command

Auto Precharge

Bank 1

Activate

Command

Bank 0

Write with

Command

Auto Precharge

Bank 0

Activate

Command

Bank2,3 = Idle

*BA0 = ”L”

REV 1.0

May, 2001

42

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/3/3)

\

= 3)

RP

, t

RCD

Begin Auto

Precharge

Bank 1

T 11 T1 2 T1 3T 1 0

(Burst length = 4, CAS latency = 3; t

Bx2

RAy

RP

t

CBx RAy

Bx0 Bx1

Ax3Ax2Ax1A x0

Bank 0

Activate

Com mand

Bank 1

R e a d wit h

C o mm a n d

Auto Precharge

OH

Begin Auto

Precharge

Bank 0

RBx

T 2 T 3 T 4T0 T1 T6 T7 T 8 T 9T5

CK3

t

RAx

RBx

CAxRAx

RRD

t

AC3

t

Bank 1

RC

t

RAS

t

RCD

t

Hi-Z

Activate

Comm and

Bank 0

R e a d w ith

Com mand

Auto Precharge

Bank 0

Activate

C o mm a n d

REV 1.0

May, 2001

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

A0-A9,

A11, A12

DQM

DQ

* BA0 = ”L”

Bank2,3 = Idle

43

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (2/2/2)

\

= 2)

RP

, t

RCD

RAy

T 1 1 T1 2 T 1 3

T10

(Burst length = 2, CAS latency = 2; t

CEH

t

Begin Auto

Precharge

Bank 1

CB x RAy

RP

t

RBx

Begin Auto

Precharge

Bank 0

RBx

CAxRAx

RC

t

RAS(min)

t

RRD

t

HZ

t

Bx1

RP

t

Bx0

HZ

t

Ax1

OH

t

AC2

t

Ax0

LZ

t

Bank 0

Activate

C o mm a n d

Bank 1

R e a d wit h

C o mm a n d

Auto Precharge

Bank 1

Activate

C o mm a n d

Bank 0

Read w ith

Com mand

Auto Precharge

REV 1.0

May, 2001

CH

T2 T3 T4

t

T1 T6 T7 T 8 T9T5

T0

CK

t

CK2

CS

t

CES

CKL

t

CKH

t

CKE

CS

RAS

CAS

WE

AH

t

RAx

AS

t

A10

* BA1

A0-A9,

DQM

A11, A12

RCD

t

Bank 0

Activate

C o mm a n d

1 clock

RAS(min)

RCD

satisfy t

Note: Must

For -260: extend t

Hi-Z

DQ

* BA0 = ”L”

Bank2,3 = Idle

44

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/2/2)

\

= 2)

RP

, t

RCD

T11 T 1 2 T1 3T 1 0

CEH

t

Begin Auto

Precharge

Bank 1

HZ

t

RAy

t

Bx1

Bank 0

Activate

Comm and

Bx0

RP

HZ

(Burst length = 2, CAS latency = 3; t

Begin Auto

Precharge

Bank 0

T 2 T 3 T 4T0 T1 T 6 T 7 T8 T9T5

CK3

t

CH

t

CS

t

CKL

t

CKH

t

CES

t

RBx

AH

t

R A x

C B x RA y

RP

t

RBx

CAxR A x

RAS

t

RRD

t

AS

t

Bank 1

R e ad wit h

C o mm a n d

OH

t

AC3

t

RC

t

RAS(min).

Ax0 Ax1

LZ

t

RCD

t

1 clock.

RCD

Hi-Z

Auto Precharge

Bank 1

Activate

Com mand

Bank 0

R e a d w ith

Com mand

Auto Precharge

Bank 0

Activate

C o mma n d

REV 1.0

May, 2001

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

A0-A9,

A11, A12

Note: Must satisfy t

DQM

DQ

Extended t

Not required for BL ≥ 4.

* BA0=” L”

Bank2,3=Idle

45

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/3/3)

\

T14

= 3)

RP

, t

RCD

CEH

t

Bx1

RP

t

Bx0

RAy

T 1 1 T1 2 T1 3T 1 0

Begin Auto

Precharge

Bank 1

CB x RAy

Bank 0

Activate

Com mand

Bank 1

Read w ith

Com mand

Auto Precharge

(Burst length = 2, CAS latency = 3; t

RP

t

OH

t

AC3

RB x

Begin Auto

Precharge

Bank 0

T 2 T 3 T4T0 T1 T6 T7 T 8 T 9T 5

CK3

t

RB x

CAxRAx

RRD

t

RC

t

RAS (mIn)

t

Ax0 Ax1

Bank 1

Activate

Com mand

Bank 0

R e a d w ith

C o mm a n d

Auto Precharge

RAS(min).

not required

RCD

t

RC D

REV 1.0

May, 2001

Note: Must satisfy t

Extended t

for BL≥4.

RAx

H i-Z

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

A0-A9,

DQM

A11, A12

DQ

Bank 0

Activate

Com mand

*BA0=” L”

Bank 2,3= Idle

46

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Mode Register Set

\

T 2 1

(CAS latency = 2)

T18 T19T15 T22T20

T 1 7

T16

T13 T14

T12

T11

T10

T8 T9T5

T7

Any

Comma nd

RSC

t

Addre ss Key

T2 T3 T4

T1 T6

T0

CK2

t

RP

t

Mode R egister

Set Com mand

All Banks

Precharge

Comma nd

REV 1.0

May, 2001

Hi-Z

CK

CKE

CS

RAS

CAS

WE

A0-A9

BA0,BA1

A12

A10,A11,

DQM

DQ

47

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power-On Sequence and Auto Refresh (CBR)

\

2 Clock min.

T16 T17 T18 T19T15 T22T20 T21

Any

Command

Address Key

Mode Register

Set Command

RC

t

T11 T12 T13 T14

T10

Command

8th Auto Refresh

Minimum of 8 Refresh Cycles are required

RP

T2 T3 T4

T1 T6 T7 T8 T9T5

CK

t

High level

is required

t

Command

1st Auto Refresh

All Banks

Precharge

Command

REV 1.0

May, 2001

T0

Inputs must be

Hi-Z

CK

CKE

CS

RAS

CAS

WE

BS

A10

A0-A9,

DQM

A11,A12

DQ

stable for 200µs

48

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Suspension / DQM During Burst Read

\

= 3)

T21

RCD

T18 T19T15 T22T20

HZ

t

T17

T16

Ax4 Ax6 Ax7

(Burst length = 8, CAS latency = 3; t

3 Cycles

T13 T14

T10

T8 T9T5 T11 T12

CEH

T7

t

Ax0 Ax1 Ax2 Ax3

CES

t

Clock Suspend

2 Cycles

Clock Suspend

1 Cycle

Clock Suspend

REV 1.0

May, 2001

CA x

T2 T3 T4

T1 T6

T0

CK3

t

RAx

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

RAx

Hi-Z

A0-A9,

DQM

A11,A12

Read

Bank 0

Command

Bank 0

Activate

Command

DQ

* BA0=” L”

Bank2,3=Idle

49

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Suspension / DQM During Burst Write

\

= 3)

RCD

T 1 6 T 1 7 T 1 8 T19T15 T 2 2T2 0 T2 1

DAx5 DAx6 DAx7

(Burst length = 8, CAS latency = 3; t

DAx3

T11 T12 T13 T 1 4

T10

DAx1 DAx2

CA x

T2 T 3 T 4

T1 T6 T7 T8 T 9T 5

T0

CK3

t

RAx

DAx0

3 Cycles

Clock Suspend

2 Cycles

Clock Suspend

1 Cycle

Clock Suspend

Write

Bank 0

Command

Bank 0

Activate

Command

REV 1.0

May, 2001

Hi-Z

CK

CS

CKE

RAS

CAS

WE

* BA1

A10

A0-A9,

DQM

A11, A12

DQ

* BA0=” L”

Bank2,3=Idle

50

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power Down Mode and Clock Suspend

\

T 2 1

Any

Com mand

NOP

CES

t

SB

T 18 T1 9T 1 5 T2 2T 2 0

T17

T 1 6

(Burst length = 4, CAS latency = 2)

T 1 3 T1 4

T12

T 1 1

T10

T8 T 9T 5

T 7

t

VALID

HZ

t

Ax2A x0 Ax1 Ax3

CK2

t

STAND B Y

PR E CH A RG E

Bank 0

Precharge

C o mm an d

End

Clock Suspension

Start

Clock Suspension

REV 1.0

May, 2001

CAxRAx

CES

t

T2 T3 T4

T1 T6

CES

T 0

t

CK

CKE

CS

RAS

CAS

WE

* BA1

RAx

A10

A0 -A9,

A11,A12

SB

t

Hi-Z

DQM

DQ

ACT IV E

Activate

Bank 0

Com mand

NOP R e a d

STAN DB Y

Bank 0

C o mm a n d

* BA0=” L”

Bank2,3=Idle

51

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Refresh (CBR)

\

T21

(CAS latency = 2)

T18 T19T15 T22T20

T17

T16

T13 T14

T12

T11

T10

T8 T9T5

T7

T2 T3 T4

T1 T6

CK2

t

RC

t

Command

Auto Refresh

RC

t

Command

RP

t

Auto Refresh

REV 1.0

May, 2001

T0

Hi-Z

CK

CKE

CS

RAS

CAS

WE

BS

A10

A0-A9,

DQM

DQ

All Banks

Precharge

Command

A11,A12

52

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Self Refresh (Entry and Exit)

\

Tm+15Tm+14

T m+1 2

Tm+9 T m+1 0Tm+6 Tm+13Tm+11

Tm+8

Any Command

Tm+7

Tm+4 Tm+5

Tm+3

Tm+2

(Note: The CK signal must be reestablished prior to CKE returning high.)

Tm+1

CES

t

Tm

T2 T3 T4

CES

t

T1

RC

t

Exit

SREX

t

SB

t

Power Down

Exit

Self Refresh

Entry

Power Down

Entry

Self Refresh

REV 1.0

May, 2001

T0

Hi-Z

CK

CKE

CS

RAS

CAS

WE

BS

A10

A0-A9,

DQM

A11,A12

All Banks

must be idle

DQ

53

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Read (Interleaving Banks) with Precharge

\

= 3)

RP

, t

RCD

t

By0

Bank 0

Precharge

C o mma n d

CBy

T16 T17 T18 T 1 9T 15 T2 2T2 0 T 21

RBy

Read

Bank 1

C o mma n d

Bank 1

Activate

C om ma n d

(Burst length = 8, CAS latency = 3;

T11 T 1 2 T 1 3 T1 4

T10

CAx

RAx

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 A x0 Ax1 Ax4 Ax5 Ax6 Ax7

AC3

t

Bank 1

Precharge

Com mand

R ea d

Bank 0

C o mma n d

Bank 0

Activate

Com mand

REV 1.0

May, 2001

T2 T 3 T 4

T 1 T6 T 7 T 8 T9T5

T0

CK3

t

RBx

H ig h

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

CBx

RCD

t

RBx

Hi-Z

A0-A9,

DQM

A11,A12

Read

Bank 1

Comm and

Bank 1

Activate

Comm and

DQ

Bank2,3=Idle

* BA0=” L”

54

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Read (Interleaving Banks) with Auto-Precharge

\

= 3)

RP

, t

RCD

CBy

Start Auto Precharge

Bank 0

RBy

By0

Ax7

Bank 1

Read w ith

Com mand

Ax4 Ax5 Ax6

Ax1

Auto Precharge

Bank 1

Activate

Com mand

(Burst length = 8,CAS latency = 3; t

T11 T 1 2 T 1 3 T1 4T10 T16 T17 T18 T19T15 T22T20 T21

Start Auto Precharge

Bank 1

CAx

Bank 0

R e ad wit h

C o mma n d

Auto Precharge

REV 1.0

May, 2001

RAx

T2 T 3 T 4T0 T1 T6 T7 T 8 T 9T 5

CK3

t

RBx

H igh

CK

CS

CKE

RAS

CAS

WE

* BA1

A10

RAx

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 A x0

AC3

t

CBx

RCD

t

RBx

H i-Z

A0-A9,

DQM

A11,A12

DQ

Bank 0

Activate

Com mand

Bank 1

Read w ith

Comm and

Auto Precharge

Bank 1

Activate

Comm and

* BA0=” L”

Bank2,3=Idle

55

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Write (Interleaving Banks) with Auto-Precharge

\

= 3)

RP

, t

RCD

CAS latency = 3; t

T16 T17 T18 T 19T15 T22T20 T 2 1

RAy

DAy2

‡

DAL

t

DAy1DAy0

Bank 0

W rite with

C o mma n d

DBx7DBx6

Auto Precharge

.

DAL

Bank 0

Activate

C o mma n d

(Burst length = 8,

‡

DAL

t

See the Clock Frequency and Latency table.

Bank may be reactivated at the completion of t

‡ Number of clocks depends on clock cycle time and speed sort.

T 1 1 T1 2 T 13 T 1 4

CBx CAy

T10

RBx

T 2 T3 T4

T 1 T 6 T7 T8 T 9T5

T0

CK3

t

RAx

High

RBx

CAX

RCD

t

RAx

DAx0 DAx1 DAx4 DAx7DAx6DAx5 DBx0 DBx3DBx2DBx1 DBx4 DBx5

Hi-Z

Bank 1

W rite with

C o mm an d

Auto Precharge

Bank 1

Activate

Com mand

Bank 0

Write with

Com mand

Auto Precharge

Bank 0

Activate

Com mand

REV 1.0

May, 2001

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

A0-A9,

DQM

A11,A12

DQ

* BA0=” L”

Bank2,3=Idle

56

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

Bank

1

NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Write (Interleaving Banks) with Precharge

\

DAy2

= 3)

RP

T21

, t

T20

RCD

T16 T17 T18 T19T15 T22

RAy

(Burst length = 8,CAS latency = 3; t

T13 T14

T12

T11

T10

CAy

DPL

t

RAy

RP

t

CBx

DAy1DAy0

DBx7DBx6

Precharge

Command

Write

Bank 0

Command

Bank 0

Activate

Command

Bank 0

Precharge

Command

Write

Bank 1

Command

REV 1.0

May, 2001

RBx

T2 T3 T4

T1 T6 T7 T8 T9T5

T0

CK3

t

RAx

High

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

RBx

CAX

RCD

t

RAx

A0-A9,

DQM

A11,A12

DAx0 DAx1 DA x4 DAx7DAx6DAx5 D Bx0 DB x3DB x2DB x1 D Bx4 D Bx5

Hi-Z

DQ

Bank 1

Activate

Command

Write

Bank 0

Command

Bank 0

Activate

Command

BA0=” L”

*

Bank2,3=Idle

57

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read / Write Cycle

\

= 3)

T21

RP

, t

RCD

T18 T19T15 T22T20

T17

T16

Bank 0

Precharge

Com mand

DA y4

Latency

T 13 T 1 4

(Burst length = 8, CAS latency = 3; t

T12

T11

T10

T8 T 9T 5

T7

T2 T 3 T 4

T1 T6

T 0

CK3

t

RA x

CAy

CAx

RA x

DAy0 DAy1 DAy3Ax0 Ax1 Ax3Ax2

Zero C lo ck

T h e Writ e D at a

is M asked with a

Write

Bank 0

Comm and

Latency

T wo C lo ck

The Read D at a

is Masked w ith a

Read

Bank 0

Com mand

Bank0

Activate

Comm and

REV 1.0

May, 2001

H i-Z

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

A0-A9,

DQM

A11,A12

DQ

* BA0=” L”

Bank2,3=Idle

58

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Interleaved Column Read Cycle

\

= 3)

T21

RP

, t

RCD

T18 T19T15 T22T20

T17

T16

(Burst length = 4, CAS latency = 3; t

T13 T14

T12

T11

T10

T8 T9T5

T7

Start Auto Precharge

Bank 0

Bank 1

Precharge

Command

CAy

CB z

CBy

CB x

Ax0 Ax3A x2Ax1 Bx0 By1By0Bx1 Bz0 Bz1 A y0 Ay3Ay2Ay1

AC3

t

Bank 0

Read with

Command

Auto Precharge

Read

Bank 1

Command

Read

Bank 1

Command

Read

Bank 1

Command

REV 1.0

May, 2001

RBx

T2 T3 T4

T1 T6

T0

CK3

t

RAx

CK

CKE

CS

RAS

CAS

WE

A10

* BA1

RBx

CAx

RCD

t

RAx

Hi-Z

A0-A9,

DQM

A11,A12

Read

Command

Activate

Command

DQ

Bank 1

Activate

Command

Bank 0

* BA0=” L”

Bank2,3=Idle

59

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Precharge after Read Burst

\

= 3)

T21

RP

, t

RCD

T18 T19T15 T22T20

T17

T16

Start

Auto Precharge

CBy

Start Auto Precharge

Bank 0

By0 By1

Bank 1

Read with

Command

Auto Precharge

RBy

T13 T14

(Burst length = 4, CAS latency = 3; t

T11 T12

T10

RBx

T2 T3 T4T0 T1 T6 T7 T8 T9T5

CK3

t

Start Auto Precharge

CAy RB y

CBx

CA x R Bx

Bank 1

Ax3Ax2A x0 Ax1 Bx3Bx2B x0 Bx1 Ay3Ay2Ay0 Ay1

Bank 1

Activate

Command

Bank 0

Read with

Command

Auto Precharge

Bank 1

Read with

Command

Auto Precharge

Bank 1

Activate

Command

Read

Bank 0

Command

REV 1.0

May, 2001

RAx

High

CK

CKE

CS

RAS

CAS

WE

* BA1

A10

RAx

Hi-Z

A0-A9,

DQM

A11,A12

DQ

Bank 0

Activate

Command

* BA0=” L”

Bank2,3=Idle

60

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Precharge after Write Burst

\

‡

D A L

t

CAz

(Burst length = 4, CAS latency = 2)

RAz

Write with

Comm and

Auto Precharge

Bank 0

Activate

Command

.

Bank 0

DAL

‡

DAL

t

CBy

RBy

T 11 T 12 T1 3 T1 4T1 0 T1 6 T17 T 18 T19T 15 T22T20 T21

RBy

‡

DAL

t

CAy

CBx

DAx3DAx2DAx1DAx0 DBx3DBx2DBx1DBx0 DAy3DAy2DAy1DAy0 DBy3DBy2DBy1DBy0 DAz3DAz2DAz1DAz0

Bank 1

Write with

Comm and

Auto Precharge

Bank 1

Activate

Command

Write with

Auto Precharge

Write with

Auto Precharge

See the Clock Frequency and Latency table.

Bank may be reactivated at the com pletion of t

‡ Num ber of clocks depends on clock cycle and speed sort.

Bank 0

Comm and

Bank 1

Comm and

REV 1.0

May, 2001

RBx

T2 T3 T4T0 T1 T6 T7 T8 T9T5

CK2

t

RAx

High

CK

CS

CKE

RAS

CAS

WE

* BA1

A10

RBx

CAx

RAx

H i-Z

A0-A9,

DQM

A11,A12

DQ

Bank 1

Activate

C o mma n d

Write

Bank 0

Command

Bank 0

Activate

C o mma n d

Bank2,3=Idle

* BA0=” L”

61

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Burst Read and Single Write Operation

\

T 1 6 T 1 7 T 1 8 T19T15 T22T 2 0 T2 1

(Burst length = 4, CAS latency = 2)

is masked

Low e r B yt e

DAz0

Ay3

Ay0 Ay1

Bank 0

Comm and

Single Write

is masked

Upper Byte

is m asked

Low e r B yt e

T13 T 1 4

CAy

T12

T 1 1

CAx CAz

T 1 0

CAw

Av3

Av2Av1

Av0 DAw0

T 2 T3 T4

T1 T 6 T7 T8 T 9T 5

CK2

t

CAv

R ea d

Bank 0

C o mma n d

DAx0

Av3

Av2Av1 A y2DAw0 Ay0 Ay3Av0

Bank 0

C o mma n d

Single Write

Bank 0

C o mm an d

Single Write

R e ad

Bank 0

C o mma n d

REV 1.0

May, 2001

T 0

Bank 0

RAv

High

CK

CS

CKE

RAS

WE

CAS

* BA1

A10

RAv

H i-Z

7

LDQM

A0-A9,

A11, A12

UDQM

- DQ

0

DQ

Activate

H i-Z

- DQ DQ

C o mma n d

15

8

* BA0=” L”

Bank2,3=Idle

62

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

CS Function (Only CS signal needs to be asserted at minimum rate)

\

= 3)

RP

, t

RCD

CAS Latency = 3, t

T16 T17 T18 T19T15 T22T20 T21

Bank A

Precharge

Command

DPL

t

Write

Bank A

Command

(at 100MHz Burst Length = 4,

T11 T12 T13 T14

T10

Ax0 DAy0 DAy3DA y2DAy1Ax3Ax2Ax1

Read

Bank A

Command

RCD

t

T2 T3 T4

T1 T6 T7 T8 T9T5

T0

CK3

t

RA x

RA x C Ax C Ay

Bank A

Activate

Command

REV 1.0

May, 2001

Low

Hi-Z

CK

CKE

CS

RAS

CAS

WE

BA0,BA1

A10, A12

A0-A9, A11

DQM

DQ

63

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)

256Mb Synchronous DRAM

Package Dimensions (400mil; 54 lead; Thin Small Outline Package)

Lead #1

22.22 ± 0.13

Detail A

10.16 ± 0.13

11.76 ± 0.20

Seating Plane

REV 1.0

May, 2001

0.80 Basic

0.35

+ 0.10

- 0.05

0.10

0.71REF

Detail A

0.25 Basic

1.20 Max

0.5 ± 0.1

0.05 Min

64

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Gage Plane

®

Nanya Technology Corporation.

©

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both. NANYA NANYA logo

Other company, product and service names may be trademarks or services maeks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com

Datasheet NT5SV64M4AT-7K, NT5SV32M8AT-75B, NT5SV32M8AT-7K, NT5SV16M16AT-75BL, NT5SV16M16AT-7KL Datasheet (NANYA)

Specifications and Main Features

Frequently Asked Questions

User Manual