Datasheet NT128D64S88A0G-75B, NT128D64S88A0G-7K, NT128D64S88A0G-8B Datasheet (NANYA)

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 16Mx8 SDRAM

Features

• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module

• 16Mx64 Double Data Rate (DDR) SDRAM DIMM
(16M X 8 SDRAM S)

• Performance :

PC1600

Speed Sort - 8B - 75B - 7K

DIMMCASLatency 2 2.5 2

f CK Clock Frequency 100 133 133 MHz

t CK Clock Cycle 10 7.5 7.5 ns

f DQ DQ Burst Frequency 200 266 266 MHz

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = 2.5Volt ±?0.2, VDD = 2.5Volt ± 0.2

• Single Pulsed RAS interface

• SDRAMs have 4 internal banks for concurrent operation

• Module has one physical bank

• Differential clock inputs

PC2100

Unit

Description

NT128D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles

• Address and control signals are fully synchronous to positive
clock edge

• Programmable Operation:

- DIMMCASLatency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 12/10/2 Addressing (row/column/bank)

• 15.6 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 66-pin TSOP Type II Package

organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.

Prior to any access operation, the device CASlatency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

Ordering Information

Part Number Speed Organization

NT128D64S88A0G-7K

NT128D64S88A0G –75B

NT128D64S88A0G –8B

143MHz (7ns @ CL = 2.5 )

133MHz (7.5ns @ CL= 2 )

133MHz (7.5ns @ CL= 2.5 )

100MHz (10ns @ CL = 2 )

125MHz (8ns @ CL = 2.5 )

100MHz (10ns @ CL = 2 )

PC2100

PC2100

PC1600

16Mx64 Gold 2.5V

Leads Power

REV1.0 / June 2001 1

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Pin Description

CK0, CK1, CK2

CK0 ,CK1,CK2

CKE0 Clock Enable

RAS Row Address Strobe
CAS Column Address Strobe VDD Power (2.5V)

WE Write Enable VDDQ Supply voltage for DQs(2.5V)

S0 Chip Selects VSS Ground

A0-A9, A11 Address Inputs NC No Connect

A10/AP Address Input/Autoprecharge SCL Serial Presence Detect Clock Input

BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output

VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs

VDDID

Differential Clock Inputs DQ0-DQ63 Data input/output

VDD Identification flag.

(Not used when VDD=VDDQ)

DQS0-DQS7,

DQS9-DQS16

VDDSPD Serial EEPROM positive power supply(2.5V)

Bidirectional data strobes

Pinout

Pin

1 VREF 93 VSS 32
2 DQ0 94 DQ4 33
3 VSS 95 DQ5 34
4 DQ1 96 VDDQ 35
5 DQS0 97 DQS9 36
6 DQ2 98 DQ6 37
7 VDD 99 DQ7 38
8 DQ3 100

9 NC 101
10 NC 102
11 VSS 103
12 DQ8 104
13 DQ9 105
14 DQS1 106
15 VDDQ 107
16 CK1 108
17 CK1 109
18 VSS 110
19 DQ10 111
20 DQ1 1 112
21 CKE0 113
22 VDDQ 114
23 DQ16 115
24 DQ17 116
25 DQS2 117
26 VSS 118
27 A9 119
28 DQ18 120
29 A7 121
30 VDDQ 122
31 DQ19 123

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

Front Pin

Back Pin

VSS 39

NC 40
NC 41
NC 42

VDDQ 43

DQ12 44
DQ13 45

DQS10 46

VDD 47
DQ14 48
DQ15 49

NC 50

VDDQ 51

NC 52

DQ20 KEY KEY 83 DQ56 175

NC 53

VSS 54

DQ21 55

A11 56

DQS11 57

VDD 58
DQ22 59

A8 60

DQ23 61

Front Pin

A5 124

DQ24 125

VSS 126

DQ25 127

DQS3 128

A4 129

VDD 130
DQ26 131
DQ27 132

A2 133

VSS 134

A1 135
NC 136
NC 137

VDD 138

NC 139
A0 140
NC 141

VSS 142

NC 143

BA1 144

DQ32 145

VDDQ 146

DQ33 147

DQS4 148

DQ34 149

VSS 150

BA0 151
DQ35 152
DQ40 153

Back Pin

VSS 62 VDDQ 154

A6 63 WE 155
DQ28 64 DQ41 156
DQ29 65 CAS 157

VDDQ 66 VSS 158

DQS12 67 DQS5 159

A3 68 DQ42 160
DQ30 69 DQ43 161

VSS 70 VDD 162

DQ31 71 NC 163

NC 72 DQ48 164

NC 73 DQ49 165

VDDQ 74 VSS 166

CK0 75 CK2 167

CK0 76 CK2 168

VSS 77 VDDQ 169

NC 78 DQS6 170

A10 79 DQ50 171

NC 80 DQ51 172

VDDQ 81 VSS 173

NC 82 VDDID 174

VSS 84 DQ57 176
DQ36 85 VDD 177
DQ37 86 DQS7 178

VDD 87 DQ58 179

DQS13 88 DQ59 180

DQ38 89 VSS 181
DQ39 90 NC 182

VSS 91 SDA 183
DQ44 92 SCL 184 VDDSPD

Front Pin

Back

RAS

DQ45

VDDQ

S0

NC

DQS14

VSS
DQ46
DQ47

NC

VDDQ

DQ52
DQ53

NC

VDD

DQS15

DQ54
DQ55

VDDQ

NC
DQ60
DQ61

VSS

DQS16

DQ62
DQ63

VDDQ

SA0
SA1
SA2

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NT128D64S88A0G

The positive line of the differential pair of system clock inputs which drives the input to the

the DDR SDRAM address and control inputs are sampled on the rising

puts which drives the input to the

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

the clocks, CKE low initiates the Power Down mode, or the Self Refresh

decoder when high. When the command decoder is disabled, new commands are ignored

define the

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

RA11)

)

ed to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

n conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

Bit input/output pins operate in the same manner as on conventional

Data strobes: Output with read data, input with write data. Edge aligned with read data,

on the system board to configure the

n is used to transfer data into or out of the SPD EEPROM. A resistor

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Input/Output Functional Description

Symbol Type Polarity

Function

CK0 , CK1, CK2 (SSTL)

CK0 ,CK1,CK2 (SSTL)

CKE0 (SSTL)

S0

RAS,CAS, WE

V REF Supply

V DDQ Supply

BA0, BA1 (SSTL)

A0 - A9
A10/AP

A11

(SSTL)

(SSTL)

(SSTL)

Positive

Edge

Negative

Edge

Active

High

Active

Low

Active

Low

-

-

on-DIMM PLL. All
edge of their associated clocks.
The negative line of the differential pair of system clock in
on-DIMM PLL.

deactivating
mode.
Enables the associated SDRAM command decoder when low and disables the command

but previous operations continue.
When sampled at the positive rising edge of the clock, RAS , CAS , WE
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs

immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0­when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9
when sampled at the rising clock edge. In addition to the column address, AP is us

autoprecharge is disabled.
During a Precharge command cycle, AP is used i

DQ0 - DQ63, (SSTL)

DQS0 - DQS7

DQS9 - DQS16

V DD , V SS Supply

SA0 – SA2 -

SDA -

SCL -

V DDSPD Supply

(SSTL)

-

Active

High

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check
DRAMs.

centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either VDD or V
Serial Presence Detect EEPROM address.
This bidirectional pi
must be connected from the SDA bus line to V DD to act as a pullup.

connected from the SCL bus time to V DD to act as a pullup.
Serial EEPROM positive power supply.

SS

REV1.0 / June 2001 3

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Functional Block Diagram ( 1 Bank, 16Mx8 DDR SDRAMs )

S0

DQS0
DQS9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS1

DQS10

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS2

DQS11

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS3

DQS12

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM CSD0DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM CS
I/O 0
I/O 1

I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS

CS

D1

DQS

D2

DQS

D3

DQS4

DQS13

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS5

DQS14

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS6

DQS15

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS7

DQS16

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM CSD7DQS
I/O 0
I/O 1

I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS

D4

DQS

CS

D5

DQS

CS

D6

S0

BA0-BA1

A0-A11

RAS
CAS CAS : SDRAMs D0 -D7

CKE0

WE

SCL

WP

Notes :

1. DQ-to-I/O wring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.

CS : SDRAMs D0 -D7
BA0 - BA1 : SDRAMs D0 -D7
A0 - A11 : SDRAMs D0 -D7
RAS : SDRAMs D0 -D7

CKE0 : SDRAMs D0 -D7
WE : SDRAMs D0 -D7

A0 A2A1

SA0 SA2SA1

SDA

REV1.0 / June 2001 4

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CK0

CK0

CK1

CK1

CK2

CK2

VDDQ

VDD

VREF

VSS

VDDID

120 ohm SDRAM x 2

120 ohm SDRAM x 3

120 ohm SDRAM x 3

D0 - D7Serial PD
D0 - D7
D0 - D7
D0 - D7

Strap: see Note 4

© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Serial Presence Detect -- Part 1 of 2

16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value Serial PD Data Entry (Hexadecimal) Note

Byte

Number of Serial PD Bytes Written during

0

Production
1 Total Number of Bytes in Serial PD device
2 Fundamental Memory Type DDR SDRAM 07
3 Number of Row Addresses on Assembly 12 0C
4 Number of Column Addresses on Assembly
5 Number of DIMM Bank 1 01

6. Data Width of Assembly X64 40
7 Data Width of Assembly (cont’) X64 00
8 Voltage Interface Level of this Assembly SSTL 2.5V 04
9 DDR SDRAM Device Cycle Time at CL=2.5 7ns 7.5ns 8ns 70 75 80

DDR SDRAM Device Access Time from

10

Clock at CL=2.5
1 1 DIMM Configuration Type Non-Parity 00
12 Refresh Rate/Type SR/1x(15.625us) 80
13 Primary DDR SDRAM Width X8 08
14 Error Checking DDR SDRAM Device Width N/A 00

DDR SDRAM Device Attr: Min C Lk Delay,
15

Random Col Access

DDR SDRAM Device Attributes:
16

Burst Length Supported

DDR SDRAM Device Attributes: Number of
17

Device Banks

DDR SDRAM Device Attributes: CAS
18

Latencies Supported
19 DDR SDRAM Device Attributes: CS Latency
20 DDR SDRAM Device Attributes: WE Latency
21 DDR SDRAM Device Attributes: Differential Clock 20
22 DDR SDRAM Device Attributes: General +/-0.2V Voltage Tolerance 00
23 Minimum Clock Cycle at CL=2 7.5ns 10ns 10ns 75 A0 A0

Maximum Data Access Time from Clock at
24

CL=2
25 Minimum Clock Cycle Time at CL=1 N/A 00

Maximum Data Access Time from Clock at
26

CL=1
27 Minimum Row Precharge Time(tRP) 20ns 20ns 20ns 50 50 50

Minimum Row Active to Row Active delay
28

(tRRD)
29 Minimum RAS to CAS delay (tRCD) 20ns 20ns 20ns 50 50 50
30 Minimum RAS Pulse Width (tRAS) 45ns 45ns 50ns 2D 2D 32
31 Module Bank Density 128MB 20

Address and Command Setup Time Before
32

Clock

Address and Command Hold Time After
33

Clock
34 Data Input Setup Time Before Clock 0.5ns 0.5ns 0.6ns 50 50 60
35 Data Input Hold Time After Clock 0.5ns 0.5ns 0.6ns 50 50 60

36-61 Reserved Undefined 00

62 SPD Revision Initial Initial Initial 00 00 00
63 Checksum Data 6C 9C 22

Description DDR266A

-7K

0.75ns 0.75ns 0.8ns 75 75 80

2/2.5 2/2.5 2/2.5 0C 0C 0C

0.75ns 0.75ns 0.8ns 75 75 80

15ns 15ns 15ns 3C 3C 3C

0.9ns 0.9ns 1.1ns 90 90 B0

0.9ns 0.9ns 1.1ns 90 90 B0

DDR266B

-75B
128 80
256 08

10 0A

1 Clock 01

2,4,8 0E

4 04

0 01
1 02

N/A 00

DDR200

-8B

DDR266A

-7K

DDR266B

-75

DDR200

-8B

REV1.0 / June 2001 5

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Serial Presence Detect -- Part 2 of 2

16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value Serial PD Data Entry (Hexadecimal)

Byte

64-71 Manufacturer’s JEDED ID Code 0B Hex bank3 7F7F7F0B00000000

72 Module Manufacturing Location N/A 00
73-90 Module Part number N/A N/A N/A 00 00 00
91-92 Module Revision Code N/A 00
93-94 Module Manufacturing Data Year/Week Code yy/ww 1,2
95-98 Module Serial Number Serial Number 00

99-255 Reserved Undefined 00

1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

Description DDR266A

-7K

DDR266B

-75B

DDR200

-8B

DDR266A

-7K

DDR266B

-75

DDR200

-8B

Note

REV1.0 / June 2001 6

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

to DQ and DQS to facilitate trace matching at

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, V

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Voltage on I/O pins relative to Vss -0.5 to VDDQ+0.5 V

OUT

V

Voltage on Input relative to Vss -0.5 to +3.6 V

IN

VDD Voltage on VDD supply relative to Vss -0.5 to +3.6 V

V

Voltage on VDDQ supply relative to Vss -0.5 to +3.6 V

DDQ

T

Operating Temperature (Ambient) 0 to+70 °C

A

T

Storage Temperature (Plastic) -55 to +150 °C

STG

PD Power Dissipation TBD W

I

Short Circuit Output Current 50 mA

OUT

Capacitance

Parameter

Input Capacitance: CK0, CK0 , CK1, CK1, CK2,CK2
Input Capacitance: A0-A11, BA0, BA1, WE ,RAS, CAS, CKE0, S0 ,
Input Capacitance: SA0-SA2, SCL
Input/Output Capacitance DQ0-63; DQS0-7, 9-16
Input/Output Capacitance: SDA

1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, T A = 25 °C, V OUT (DC) = VDDQ/2 , VOUT (Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading
the board level.

Symbol Max. Units Notes

CI1 12 pF 1
CI2 30 pF 1

CI4 9 pF 1
CIO1 7 pF 1,2
CIO3 11 pF

REV1.0 / June 2001 7

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

DC Electrical Characteristics and Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol Parameter Min Max Units Notes

VDD

VDDQ

VSS , VSSQ Supply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ

VTT I/O Termination Voltage (System) VREF – 0.04 VREF + 0.04 V 1,3

VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3

VIL(DC) Input Low (Logic0) Voltage -0.3 VREF- 0.15

VIN(DC) Input Voltage Level, CK andCK Inputs -0.3 VDDQ + 0.3
VID(DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6

II

IOZ

IOH

Supply Voltage 2.3 2.7 V 1
I/O Supply Voltage 2.3 2.7 V 1

V 1,2

V 1
V 1
V 1
V 1,4

Address and

control inputs

Input Leakage Current
Any input 0V < = VIN < = VDD
(All other pins not under test = 0V)

Output Leakage Current
(DQs are disabled; 0V < = Vout < = VDDQ

Output High Current
(VOUT = VDDQ -0.373V, min VREF , min VTT ) -16.8

DQ0-63;

DQS0-7, 9-16

CK0, CK0

CK1, CK1

CK2, CK2

DQ0-63;

DQS0-7, 9-16

SDA

-40

-5

-15

-5

-1

40

5

15

5 uA 1

1

- mA 1

uA 1

IOL

1. Inputs are not recognized as valid until V REF stabilizes.

2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on V REF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,
and must track variations in the DC level of V REF .

4. VID is the magnitude of the difference between the input level on CK and the input level onCK .

Output Low Current
(VOUT = 0.373, max VREF , max VTT ) 16.8

- mA 1

REV1.0 / June 2001 8

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to V SS .

2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.

AC Output Load Circuits

V

TT

50 ohms

Output

V

OUT

30 pF

Timing Reference Point

AC Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol Parameter/Condition Min Max Unit Notes

V IH(AC) Input High (Logic 1) Voltage. V REF + 0.31 V 1, 2

V IL(AC) Input Low (Logic 0) Voltage. V REF ?- 0.31 V 1, 2

V ID(AC) Input Differential Voltage, CK and CK Inputs 0.62 V DDQ + 0.6 V 1, 2, 3

V IX(AC) Input Differential Pair Cross Point Voltage, CK andCK Inputs (0.5*VDDQ ) - 0.2 (0.5*VDDQ ) +? 0.2 V 1, 2, 4

1. Input slew rate = 1V/ ns .

2. Inputs are not recognized as valid until V REF stabilizes.

3. V ID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

REV1.0 / June 2001 9

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

; DQ, DM, and DQS inputs changing twice per clock cycle;

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Operating, Standby, and Refresh Currents

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Operating Current: one bank; active / precharge; t RC =t RC (MIN) ;

I DD0

tCK = tCK (MIN)
address and control inputs changing once per clock cycle
Operating Current: one bank; active / read / precharge; Burst = 2;

I DD1

t RC = t RC (MIN) ; CL = 2.5; t CK = t CK (MIN) ;I OUT = 0mA;
address and control inputs changing once per clock cycle

I DD2P

I DD2N

I DD3P

I DD3N

I DD4R

I DD4W

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns .

3. Enables on-chip refresh and address counters.

4. Current at 15.625 µs is time averaged value of I DD5 at t RFC MIN and I DD2P over 15.625 µs.

Precharge Power-Down Standby Current:
all banks idle; power-down mode; CKE <= VIL (MAX ) ; t CK = t CK (MIN)
Idle Standby Current: CS >= V IH (MIN) ; all banks idle; CKE >= V IH(MIN) ;
t CK = t CK (MIN) ; address and control inputs changing once per clock cycle
Active Power-Down Standby Current: one bank active;
power-down mode; CKE <= V IL (MAX) ; t CK = t CK (MIN)
Active Standby Current: one bank; active / precharge; CS >= V IH (MIN) ;
CKE >= VIH (MIN) ; t RC = t RAS (MAX) ; t CK = t CK (MIN) ; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
t CK = t CK (MIN) ; I OUT = 0mA
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
t CK = t CK (MIN)

I DD5 Auto-Refresh Current:

Self-Refresh Current: CKE <= ?0.2V 16 16 mA 1,2,3

I DD6

Parameter/Condition PC1600 PC2100 Unit Notes

600 680 mA 1,2

720 880 mA 1,2

120 120 mA 1,2

240 280 mA 1,2

120 120 mA 1,2

400 480 mA 1,2

1040 1320 mA 1,2

920 1200 mA 1,2

t RC = t RFC (MIN) 1280 1360 mA 1,2

t RC = 15.625 µs 126 126 mA 1,2,4

REV1.0 / June 2001 10

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

AC Timing Speci fications for DDR SDRAM Devices Used on Module

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

Symbol Parameter

tAC DQ output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1,2,3,4

tDQSCK DQS output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1,2,3,4

tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1,2,3,4

tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1,2,3,4
tCK CL=2.5 7 12 7.5 12 8 12 ns 1,2,3,4
tCK

tDH DQ and DM input hold time 0.5 0.5 0.6 ns

Clock cycle time

CL=2 7.5 12 10 12 10 12 ns 1,2,3,4

-7K -75B -8B

Min. Max. M in. Max. Min. Max.

Unit Notes

1,2,3,4
, 18,19

tDS DQ and DM input setup time 0.5 0.5 0.6 ns

tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1,2,3,4

tHZ Data-out high-impedance time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

tLZ Data-out low-impedance time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

tDQSQ

tDQSQA DQS-DQ skew (DQS & all DQ signals) 0.5 0.5 0.6 ns 1,2,3,4

tHP

tQH Data output hold time from DQS

tDQSS

tDQSL,H

tDSS

tDSH
tMRD Mode register set command cycle time 14 15 16 ns 1,2,3,4

tWPRES Write preamble setup time 0 0 0 ns

tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK

tWPRE Write preamble 0.25 0.25 0.25 tCK 1,2,3,4

tIH

tIS

tIH

DQS-DQ skew (DQS & associated DQ
signals)

Minimum half clk period for any given cycle;
defined by clk high(tCH )
or clk low (tCL ) time

Write command to 1st DQS latching
transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)

Address and control input hold time
(fast slew rate)

Address and control input setup time
(fast slew rate)

Address and control input hold time
(slow slew rate)

0.5 0.5 0.6 ns 1,2,3,4

tCH

or

tCL

tHP -

0.75n
s

0.75 1.25 0.75 1.25 0.75 1.25 tCK 1,2,3,4

0.35 0.35 0.35 tCK 1,2,3,4

0.2 0.2 0.2 tCK 1,2,3,4

0.2 0.2 0.2 tCK 1,2,3,4

0.9 1.1 1.1 ns

0.9 1.1 1.1 ns

1.0 1.1 1.1 ns

tCH

or

tCL

tHP -

0.75n
s

tCH

or

tCL

tHP -

1.0ns

tCK 1,2,3,4

tCK 1,2,3,4

1,2,3,4

,18,19

1, 2, 3,

4, 5

1, 2, 3,

4, 5

1, 2, 3,

4, 7

1, 2, 3,

4, 6

2, 3, 4,
11, 13,

14
2, 3, 4,
11, 13,

14
2, 3, 4,
12, 13,

14, 17

REV1.0 / June 2001 11

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

Symbol

tIS

tIPW Input pulse width 2.2 2.2 - ns
tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK

tRPST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK
tRAS Active to Precharge command 45 120,000

tRC

tRFC

tRCD Active to Read or Write delay 20 20 20 ns

tRAP

tRP Precharge command period 20 20 20 ns

tRRD

tWR Write recovery time 15 15 15 ns

tDAL

tWTR Internal write to read command delay

tXSNR

tXSRD Exit self-refresh to read command 200 200 200 tCK 1,2,3,4
tREFI Average Periodic Refresh Interval 15.6 15.6 15.6 µs

Address and control input setup time
(slow slewrate)

Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period

Active to Read Command with
Autoprecharge

Active bank A to Active bank B
command

Auto precharge write recovery +
precharge time

Exit self-refresh to non-read
command

Parameter

-7K -75B -8B

Min. Max. Min. Max. Min. Max.

1.0 1.0 1.1 ns

45 120,000

65 65 70 ns

75 75 80

20 20 20 ns

15 15 15 ns

(tWR/

tCK )

+
(tRP/
tCK )

1 1 1 tCK 1,2,3,4

75 75 80 ns 1,2,3,4

(tWR/

tCK )

+

(tRP /

tCK )

50 120,000 ns

(tWR/

tCK )

+

(tRP /

tCK )

Unit Notes

ns 1,2,3,4

tCK

2, 3, 4,
12, 13,

14, 17

2, 3, 4,

1,2,3,4
1,2,3,4
1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1, 2, 3,

4, 16

1, 2, 3,

4, 8

14

REV1.0 / June 2001 12

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

AC Timing Specification Notes

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK ) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK , is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .

5. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on t DQSS .

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.

9. QFC is enabled as soon as possible after the rising CK edge that registers the Write command.

10.QFC is disabled as soon as possible after the last valid DQS edge transitions Low.

11. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL(AC).

12. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

13. CK/CK slew rates are >= 1.0 V/ns.

14. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

15. The specified timing is guaranteed assuming QFC is connected to a test load consisting of 20 pF to ground and a pull up resistor of

150 ohms to Vddq .

16. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL = 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

17. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate ?Delta ( tIS ) Delta ( tIH ) Unit Note

0.5 V/ns 0 0 ps 1,2

0.4 V/ns +50 0 ps 1,2

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

18. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

19. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each

0.3 V/ns +100 0 ps 1,2

for rising transitions.

Input Slew Rate Delta ( tDS ) Delta ( tDH ) Unit Note

0.5 V/ns 0 0 ps 1,2

0.4 V/ns +75 +75 ps 1,2

0.3 V/ns +150 +150 ps 1,2

rising transitions.

Delta Rise and Fall Rate Delta ( tDS ) Delta ( tDH ) Unit Note

0.0 ns/V 0 0 ps 1,2,3,4

0.25 ns/V +50 +50 ps 1,2,3,4

0.5 ns/V +100 +100 ps 1,2,3,4

for rising transitions.

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.

device.

REV1.0 / June 2001 13

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

AC Timing for PC2100 - Applicable Specifications Expressed in Clock Cycles

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol Parameter

tMRD Mode register set command cycle time 2 tCK 1,2,3,4

tWPRE Write preamble 0.25 tCK 1,2,3,4

tRAS Active to Precharge command 6 16000 tCK 1,2,3,4

tRC Active to Active/Auto-refresh command period 9 tCK 1,2,3,4
tRFC
tRCD Active to Read or Write delay 3 tCK 1,2,3,4

tRAP Active to Read Command with Autoprecharge 3 tCK 1,2,3,4

tRP Precharge command period 3 tCK 1,2,3,4

tRRD Active bank A to Active bank B command 2 tCK 1,2,3,4

tWR Write recovery time 2 tCK 1,2,3,4,5

tDAL Auto precharge write recovery + precharge time 5 tCK 1, 2, 3,4

tWTR Internal write to read command delay 1 tCK 1, 2, 3,4

tXSNR Exit self-refresh to non-read command 10 tCK 1, 2, 3,4
tXSRD Exit self-refresh to read command 200 tCK 1, 2, 3,4

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK ) is the point at which CK andCK cross: the input reference level
for signals other than CK/CK , is V REF.

3. Inputs are not recognized as valid until V REF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V TT .

5. tHZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

Auto-refresh to Active/Auto-refresh
command period

PC2100 @ CL = 2.5

Min. Max.

10 tCK 1,2,3,4

Unit Note

REV1.0 / June 2001 14

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© NANYA TECHNOLOGY CORP.

NT128D64S88A0G

D1 D2 D3 D4 D5 D6 D7

128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM

Package Dimensions

D0

REV1.0 / June 2001 15

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

© NANYA TECHNOLOGY CORP.