Page 1
NR8576 Series
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
The NR8576 Series devices are serial-interface type
real-time clock module ICs with built-in crystal
oscillator elements. They feature timer counter circuits that keep track of time from the current second
to the current year, automatic leap-year adjustment,
and a supply voltage detect function. Also, a 32.768
kHz/1 Hz select output function is incorporated for
independent hardware control. They are available in
compact 14-pin SOPs (NR8576A × ) and miniature
18-pin SOPs (NR8576B × ).
FEATURES
Crystal oscillator element built-in for adjustment-
■
free use
■
Timer counters for second, minute, hour, day, day
of the week, month, and year
■
2.5 to 5.5 V operating voltage range
■
1.7 ± 0.3 V supply voltage detection threshold
■
1.0 µA at 3.0 V (typ) current consumption
■
Automatic leap-year calendar adjustment
■
32.768 kHz and 1 Hz output selectable
■
Package
• 14-pin SOP (NR8576A × )
• 18-pin SOP (NR8576B × )
SERIES CONFIGURATION
PINOUTS
14-pin SOP
18-pin SOP
FSEL
Real-time Clock Modules
1
VSS
2
N.C
3
CE
4
FSEL
5
WR
6
FOE
7
N.C N.C
1
N.C
2
N.C
3
N.C
4
N.C
5
FOE
6
WR
7
811
CE
VSS
14
NR8576A
NR8576B
FOUT
13
N.C
12
N.C
11
DATA
10
CLK
9
VDD
8
18
N.C
17
N.C
16
N.C
15
N.C
VDD
14
N.C
13
12
CLK
DATA
109
FOUT
Device Package Frequency deviation
NR8576AA 14-pin SOP 5 ± 12 ppm
NR8576AB 14-pin SOP 5 ± 23 ppm
NR8576BA 18-pin SOP 5 ± 12 ppm
NR8576BB 18-pin SOP 5 ± 23 ppm
NIPPON PRECISION CIRCUITS—1
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PACKAGE DIMENSIONS
Unit: mm
NR8576 Series
14-pin SOP
10.1 0.2
1.27
0.35 0.1
BLOCK DIAGRAM
5.0
3.2 0.1
7.4 0.2
0.10 0.05
010
0.15
0.6 0.2
18-pin SOP
1.27
11.4 0.2
0.4 0.1
5.4
1.8 0.1
010
7.8 0.2
0.6 0.2
0.15
0.05 0.05
FOUT
FSEL
FOE
DATA
CLK
WR
CE
32.768kHz
OSC
Output
Controller
I/O
Controller
VDD VSS
Divider Timer Counter
Shift Register
Voltage
Detect
Control
Circuit
NIPPON PRECISION CIRCUITS—2
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−
−
−
−
°
°
−
°
NR8576 Series
PIN DESCRIPTION
Name I/O Description
VSS – Ground
CE I
FSEL I
WR I
FOE I
VDD –
CLK I
DATA I/O Data read and write input/output
FOUT O
N. C – No connection. Leave open for normal use.
Chip enable.
HIGH: Enable
LOW: DATA goes high impedance; input on WR, CLK, and DATA stops; and the TM bit is cleared.
FOUT output frequency select.
HIGH: 1 Hz
LOW: 32.768 kHz
DATA input/output control switch.
HIGH: Data input mode (RTC write)
LOW: Data output mode (RTC read)
FOUT output enable control.
HIGH: The frequency selected by FSEL is output on FOUT.
LOW: FOUT goes high impedance.
Supply voltage.
Connect a ≥ 0.1 µF capacitor between VDD and VSS.
System clock input.
Data is input (RTC write mode) and output (RTC read mode) on the rising edge of CLK.
Frequency output (output controlled by FOE and frequency selected by FSEL).
In 1 Hz output mode, the 1 Hz signal is synchronized to the internal 1 second signal.
FOUT output is not affected by the CE signal.
SPECIFICATIONS
Absolute Maximum Ratings
V
= 0 V
SS
Parameter Symbol Condition Rating Unit
Supply voltage range V
Input voltage range V
Output voltage range V
Storage temperature range T
Soldering temperature T
Soldering time t
DD
IN
OUT
stg
sld
sld
Recommended Operating Conditions
V
= 0 V
SS
Parameter Symbol Condition Rating Unit
Supply voltage range V
Clock supply voltage range V
Operating temperature range T
DD
CLK
opr
T
a
T
a
T
a
= 25 ° C
= 25 ° CV
= 25 ° CV
0.3 to 7.0 V
SS
SS
0.3 to V
0.3 to V
+ 0.3 V
DD
+ 0.3 V
DD
55 to 125
260
10 s
2.5 to 5.5 V
1.4 to 5.5 V
40 to 85
C
C
C
NIPPON PRECISION CIRCUITS—3
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Oscillator Characteristics
Parameter Symbol Condition Rating Unit
Frequency deviation
Frequency temperature characteristic T
Frequency voltage characteristic f/V
Oscillator start time t
Aging f
DC Electrical Characteristics
f/f
STA
∆
−
−
NR8576 Series
T
= 25 ° C,
O
op
A
a
V
= 5.0 V
DD
T
= − 10 to 70 ° C,
a
V
= 5.0 V , 25 ° C std
DD
= 25 ° C,
T
a
V
= 2.0 to 5.5 V
DD
T
= 25 ° C, V
a
T
= 25 ° C, V
a
first year
NR8576 × A 5 ± 12 ppm
NR8576 × B 5 ± 23 ppm
+10/ − 120 ppm
±2 ppm/V
= 2.5 V 3 s
DD
= 5.0 V ,
DD
±5 ppm
V
= 0 V, V
SS
= 5.0 V ± 10%, T
DD
= − 40 to 85 ° C unless otherwise noted
a
Parameter Symbol Condition
I
DD1
I
DD2
I
Current consumption
DD3
I
DD4
I
DD5
I
DD6
HIGH-level input voltage V
LOW-level input voltage V
Input OFF leakage current I
OFF
V
HIGH-level output voltage
V
LOW-level output voltage
V
V
Output load fanout N/C
I
Output leakage current
Supply voltage detect
threshold voltage
OZH
I
OZL
V
V
= 5.0 V
DD
V
= 3.0 V – 1.0 2.0 µA
DD
V
= 2.0 V – 0.5 1.0 µA
DD
V
= 5.0 V
DD
V
= 3.0 V – 2.5 6.5 µA
DD
V
= 2.0 V – 1.5 4.0 µA
DD
CE, FSEL, WR, FOE, CLK, DATA 0.8V
IH
CE, FSEL, WR, FOE, CLK, DATA – – 0.2V
IL
CE, FSEL, WR, FOE, CLK;
V
= V
IN
V
OH1
OH2
OL1
OL2
L
DT
= 5.0 V
DD
V
= 3.0 V 2.0 – – V
DD
V
= 5.0 V
DD
V
= 3.0 V – – 0.8 V
DD
FOUT 2 LSTTL/30 pF max.
V
OUT
V
OUT
CE = V
SS
FSEL = V
FOUT: floating
CE = V
SS
FSEL = V
FOUT: 32 kHz output
or V
DD
SS
I
= − 1.0 mA;
OH
DATA, FOUT
I
= 1.0 mA;
OL
DATA, FOUT
= 5.5 V; DATA, FOUT
= 0 V; DATA, FOUT
, FOE = V
,
DD
, FOE = V
,
SS
SS
DD
Rating
Unit
min typ max
,
,
– 1.5 3.0 µA
– 4.0 10.0 µA
DD
––V
DD
V
– – 0.5 µA
4.5 – – V
– – 0.5 V
1.0 – 1.0 µA
1.0 – 1.0 µA
1.4 1.7 2.0 V
NIPPON PRECISION CIRCUITS—4
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AC Characteristics
V
= 3.0 V, V
DD
CLK clock period t
CLK LOW-level pulsewidth t
CLK HIGH-level pulsewidth t
CE setup time t
CE hold time t
CE enable time t
Write data setup time t
Write data hold time t
WR setup time t
WR hold time t
DATA output delay time t
DATA output floating time t
Clock rise time t
Clock f all time t
FOUT rise time (C
FOUT fall time (C
Disable time (C
Enable time (C
FOUT duty cycle (C
Wait time t
= 0 V, T
SS
= 25 ° C unless otherwise noted
a
Parameter Symbol
= 30 pF) t
L
= 30 pF) t
L
= 30 pF)
L
= 30 pF)
L
= 30 pF) Duty 40 60 40 60 %
L
NR8576 Series
CLK
CLKL
CLKH
CES
CEH
CE
SD
HD
WRS
WRH
DATD
DZ
r1
f1
r2
f2
t
HZ
t
LZ
t
ZH
t
ZL
RCV
Rating
= 5 V ± 10% V
DD
= 3 V ± 10%
DD
UnitV
min ma x min max
0.75 7800 1.5 7800 µs
0.375 3900 0.75 3900 µs
0.375 3900 0.75 3900 µs
0.375 3900 0.75 3900 µs
0.375 – 0.75 – µ s
– 0.9 – 0.9 s
0.1 – 0.2 – µs
0.1 – 0.1 – µs
100 – 100 – ns
100 – 100 – ns
– 0.2 – 0.4 µs
– 0.1 – 0.2 µs
–50–100ns
–50–100ns
– 100 – 200 ns
– 100 – 200 ns
– 100 – 200 ns
– 100 – 200 ns
– 100 – 200 ns
– 100 – 200 ns
0.95 – 1.9 – µs
NIPPON PRECISION CIRCUITS—5
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Timing Diagrams
Data read
WR
NR8576 Series
CE
t
CE
CLK
DATA
Data write
WR
CE
tWRS
tWRS
tCES
tCLK
tCLKH
tCLKL tf1 tr1
tDATD
tWRH
tCEH
tRCV
tDZ
t
CE
tWRH
CLK
DATA
tCES
tSD
tCLKH
tHD
tCLK
tCLKL
tf1 tr1
tCEH
tRCV
NIPPON PRECISION CIRCUITS—6
Page 7
FOUT
FOUT
NR8576 Series
t
f2
90%
10%
t
r2
tH
50%
Disable/Enable
FOE
FOUT
FOE
50%
50%
tZH
tZL
10%
t
t
HZ
50%
90%
LZ
t
50%
t
H
Duty= X 100(%)
t
FOUT
90%
10%
Note that FOE and FSEL do not have chatter elimination circuits. Consequently, switching either FOE or
FSEL during 32 kHz mode operation may generate chatter noise on the FOUT output. Also, note that the 1 Hz
and 32 kHz oscillators are not synchronized to each other, so switching intervals shortens the duty cycle.
Accordingly, a wait time (≥ chattering time + output frequency period) should be incorporated when switching
intervals.
NIPPON PRECISION CIRCUITS—7
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NR8576 Series
FUNCTIONAL DESCRIPTION
Timer data configuration
■ Counter data in BCD code format
■ Automatic long/short month and leap-year adjustment
■ 24-hour time display
■ LSB first write and read data
MSB LSB
Second ( 0 to 59 )
Minute ( 0 to 59 )
Hour ( 0 to 23 )
Week ( 1 to 7 )
Day ( 1 to 31 )
Month ( 1 to 12 )
Year ( 0 to 99 )
FDT
∗
∗ ∗
∗ ∗
TM
y80 y40 y20 y10 y8 y1
S40 S20 S10 S8 S1S2S4
mi40 mi20 mi10 mi8 mi1mi2mi4
h20 h10 h8 h1h2h4
∗
d20 d10 d8 d1d2d4
∗
∗
mo10 mo8 mo1mo2mo4
y4
y2
w1w2w4
1. * bit: Optional write bits.
2. FDT bit: Supply voltage detect bit
• The FDT bit is set to 1 when the voltage between VDD and VSS falls below 1.7 ± 0.3 V.
• The FDT bit is reset to 0 for data reads longer than 48 bits. Note that the FDT bit is not reset to 0 for data
reads of 47 bits or less.
• The read/write data bits should be should be set to 0. After the supply voltage is applied, the FDT bit
should be set to 0.
DET
VDD
V
0.5 second 0.5 second
Detected Pulse
CE
(READ MODE)
FDT
3. TM bit: Factory test bit. Should be set to 0 for normal use.
NIPPON PRECISION CIRCUITS—8
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Data Read
CLK
CE
WR
NR8576 Series
1 2 3 52 53 54 54+n
DATA
OUTPUT MODE
S1
FDTS40S20S10S8S4S2 y80y40y20y10y8
second
Data is output when WR is LOW and CE is HIGH.
Time and calendar data is loaded into shift registers
on the first rising edge of the clock CLK, and the seconds’ digit LSB is output on DATA.
The data is then loaded and shifted in the sequence
second, minute, hour, week, day, and month on the
rising edge of CLK, and output on DATA. The output
data is valid after 52 rising edges of the clock; data
input after 52 cycles does not alter the first 52 bits of
valid data.
year
NON CHANGE
OUTPUT DATA
Within the 52 cycles of valid data, data already input
can be output if there is a falling edge of CE after the
corresponding number of cycles. For example, the
data comprising the second-to-week is output is CE
goes LOW after 28 clock cycles.
For continuous data reads, a wait time (t
RCV
) is
required before the next data cycle if CE has gone
LOW.
Note that if an update operation (a 1 s carry) occurs
during a data read, an error of −1 s in the read data is
generated.
The data read time should be completed after
tCE ≤ 0.9 s.
NIPPON PRECISION CIRCUITS—9
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Data Write
CLK
CE
WR
NR8576 Series
1 2 3 52 53 54 54+n
DATA
INPUT MODE
S1
FDTS40S20S10S8S4S2 y80y40y20y10y8
second
Data is input when WR is HIGH and CE is HIGH.
The seconds’ digit signal to the timer counter stops
on the first falling edge of CLK and the counter
remains stopped until the next rising edge of CE. The
1 Hz to 128 Hz frequency divider step counters are
reset during the interval between the first and second
rising edges of CLK.
The data is then input on DATA into the shift register, starting with seconds’ digit LSB synchronized
with the rising edge of CLK.
After the final data is input into the shift register following 52 cycles, the shift register contents are trans-
year
ferred to the timer counters. Note that a data write
must contain 52 bits of input data. If CE goes LOW
before 52 bits are input, the input data is invalid. If
the input data exceeds 52 bits, data from the 53rd bit
is ignored (the first 52 bits remain valid).
The data write time should be completed after
tCE ≤ 0.9 s.
If a data read occurs immediately after a data write, a
wait time (t
) is required if CE has gone LOW.
RCV
Note that writing null data will cause incorrect operation. All bits must be valid data bits.
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
NIPPON PRECISION CIRCUITS INC.
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9603CE 1997.06
NIPPON PRECISION CIRCUITS—10
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