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NMC27C64Q150

Datasheet NMC27C64N200, NMC27C64NE200, NMC27C64Q150, NMC27C64Q250, NMC27C64QE200 Datasheet (Fairchild Semiconductor)

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Page 1
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
General Description
The NMC27C64 is a 64K UV erasable, electrically reprogrammable and one-time programmable (OTP) CMOS EPROM ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C64 is designed to operate with a single +5V power supply with ±10% tolerance. The CMOS design allows the part to operate over extended and military temperature ranges.
The NMC27C64Q is packaged in a 28-pin dual-in-line package with a quartz window. The quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written electrically into the device by following the programming procedure.
The NMC27C64N is packaged in a 28-pin dual-in-line plastic molded package without a transparent lid. This part is ideally
Block Diagram
January 1999
suited for high volume production applications where cost is an important factor and programming only needs to be done once.
This family of EPROMs are fabricated with Fairchild’s proprietary, time proven CMOS double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability.
Features
■ High performance CMOS —150 ns access time
■ JEDEC standard pin configuration —28-pin Plastic DIP package —28-pin CERDIP package
■ Drop-in replacement for 27C64 or 2764
■ Manufacturers identification code
DS008634-1
Output Enable,
Chip Enable, and
Program Logic
Y Decoder
X Decoder
. . . . . . . . .
Output Buffers
65,536-Bit Cell Matrix
Data Outputs O0 - O
7
V
CC
GND
V
PP
OE
PGM
CE
A0 - A
12
Address
Inputs
© 1998 Fairchild Semiconductor Corporation
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Connection Diagram
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64 pins.
V
CC
PGM NC A
8
A
9
A
11
OE A
10
CE O
7
O
6
O
5
O
4
O
3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V
PP
A
12 A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C512
27512
27C256
27256
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
NMC27C64
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C32
2732
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C16
2716
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C128
27128
27C256
27256
27C512
27512
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE O
7
O
6
O
5
O
4
O
3
V
CC
PGM
A
13
A
8
A
9
A
11
OE
A
10
CE O
7
O
6
O
5
O
4
O
3
V
CC
A
8
A
9
V
PP
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
A
8
A
9
A
11
OE/V
PP
A
10
CE O
7
O
6
O
5
O
4
O
3
27C16
2716
27C32
2732
27C128
27128
DS008634-2
Pin Names
A0–A12 Addresses
CE Chip Enable OE Output Enable
O0 –O
7
Outputs
PGM Program
NC No Connect V
PP
Programming Voltage
V
CC
Power Supply
GND Ground
Commercial Temperature Range V
CC
= 5V ±10%
Parameter/Order Number Access Time (ns)
NMC27C64Q, N 150 150 NMC27C64Q, N 200 200
Extended Temp Range (-40°C to +85°C) V
CC
= 5V ±10%
Parameter/Order Number Access Time (ns)
NMC27C64QE, NE200 200
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
READ OPERATION DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
I
LI
Input Load Current VIN = VCC or GND 10 µA
I
LO
Output Leakage Current V
OUT
= VCC or GND, CE = V
IH
10 µA
I
CC1
V
CC
Current (Active) CE = VIL ,f=5 MHz 5 20 mA
(Note 9) TTL Inputs Inputs = VIH or VIL, I/O = 0 mA
I
CC2
VCC Current (Active) CE = GND, f = 5 MHz 3 10 mA
(Note 9) CMOS Inputs Inputs = VCC or GND, I/O = 0 mA
I
CCSB1
V
CC
Current (Standby) CE = V
IH
0.1 1 mA
TTL Inputs
I
CCSB2
VCC Current (Standby) CE = V
CC
0.5 100 µA
CMOS Inputs
I
PP
VPP Load Current VPP = V
CC
10 µA
V
IL
Input Low Voltage -0.1 0.8 V
V
IH
Input High Voltage 2.0 VCC +1 V
V
OL1
Output Low Voltage IOL = 2.1 mA 0.45 V
V
OH1
Output High Voltage IOH = -400 µA 2.4 V
V
OL2
Output Low Voltage IOL = 0 µA 0.1 V
V
OH2
Output High Voltage IOH = 0 µAV
CC
- 0.1 V
AC Electrical Characteristics
NMC27C64
Symbol Parameter Conditions 150 200, E200 Units
Min Max Min Max
t
ACC
Address to CE = OE = V
IL
150 200 ns
Output Delay PGM = V
IH
t
CE
CE to Output Delay
OE = VIL, PGM = V
IH
150 200 ns
t
OE
OE to Output Delay
CE = VIL, PGM = V
IH
60 60 ns
t
DF
OE High to Output Float CE = VIL, PGM = V
IH
0 60 0 60 ns
t
CF
CE High to Output Float OE = VIL, PGM = V
IH
0 60 0 60 ns
t
OH
Output Hold from CE = OE = V
IL
Addresses, CE or OE , PGM = V
IH
00ns
Whichever Occurred First
Absolute Maximum Ratings (Note 1)
Temperature Under Bias -55°C to +125°C Storage Temperature -65°C to +150°C All Input Voltages except A9
with Respect to Ground (Note 10) +6.5V to -0.6V
All Output Voltages
with Respect to Ground (Note 10)VCC +1.0V to GND -0.6V
VPP Supply Voltage and A
9
with Respect to Ground During Programming +14.0V to -0.6V
VCC Supply Voltage with
Respect to Ground +7.0V to -0.6V
Power Dissipation 1.0W Lead Temperature
(Soldering, 10 sec.) 300°C
ESD Rating
(Mil Spec 883C, Method 3015.2) 2000V
Operating Conditions (Note 7)
Temperature Range
NMC27C64Q 150, 200 0°C to +70°C NMC27C64N 150, 200 NMC27C64QE 200 -40°C to +85°C NMC27C64NE 200
VCC Power Supply +5V ±10%
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Capacitance TA = +25˚C, f = 1 MHz (Note 2) NMC27C64Q
Symbol Parameter Conditions Typ Max Units
C
IN
Input Capacitance VIN = 0V 6 8 pF
C
OUT
Output Capacitance V
OUT
= 0V 9 12 pF
Capacitance TA = +25˚C, f = 1 MHz (Note 2) NMC27C64N
Symbol Parameter Conditions Typ Max Units
C
IN
Input Capacitance VIN = 0V 5 10 pF
C
OUT
Output Capacitance V
OUT
= 0V 8 10 pF
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level
Inputs 0.8V and 2V Outputs 0.8V and 2V
AC Waveforms (Note 6) (Note 9)
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t
ACC
- tOE after the falling edge of CE without impacting t
ACC
.
Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE ® , the measured V
OH1
(DC) ˛ 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Address Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2V
0.8V
(Note 3)
(Note 3)
t
DF
t
CF
(Notes 4, 5)
(Notes 4, 5)
t
OH
Hi-Z
t
OE
ACC
t
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Programming Characteristics (Note 11) (Note 12) (Note 13) (Note 14)
Symbol Parameter Conditions Min Typ Max Units
t
AS
Address Setup Time 2 µs
t
OES
OE Setup Time 2 µs
t
CES
CE Setup Time 2 µs
t
DS
Data Setup Time 2 µs
t
VPS
VPP Setup Time 2 µs
t
VCS
VCC Setup Time 2 µs
t
AH
Address Hold Time 0 µs
t
DH
Data Hold Time 2 µs
t
DF
Output Enable to CE = V
IL
0 130 ns
Output Float Delay
t
PW
Program Pulse Width 0.45 0.5 0.55 ms
t
OE
Data Valid from OE CE = V
IL
150 ns
I
PP
VPP Supply Current During CE = V
IL
30 mA
Programming Pulse PGM = V
IL
I
CC
VCC Supply Current 10 mA
T
A
Temperature Ambient 20 25 30 ˚C
V
CC
Power Supply Voltage 5.75 6.0 6.25 V
V
PP
Programming Supply Voltage 12.2 13.0 13.3 V
t
FR
Input Rise, Fall Time 5 ns
V
IL
Input Low Voltage 0.0 0.45 V
V
IH
Input High Voltage 2.4 4.0 V
t
IN
Input Timing Reference Voltage 0.8 1.5 2.0 V
t
OUT
Output Timing Reference Voltage 0.8 1.5 2.0 V
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Programming Waveforms (Note 13)
Note 11:Fairchild’s standard product warranty applies to devices programmed to specifications described herein. Note 12:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC. Note 13:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device.
Note 14:Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.
t
AS
t
AH
Program
Program
Verify
Address N
t
DF
Data Out Valid
Add N
Data In Stable
Add N
Hi-Z
t
DS
t
DH
t
VCS
t
VPS
t
CES
t
PW
t
OES
t
OE
2V
0.8V
2V
0.8V
2V
0.8V
2V
0.8V
6.0V
13.0V
0.8V
ADDRESS
DATA
V
CC
CE
OE
V
PP
PGM
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Fast Programming Algorithm Flow Chart
Yes
No
Start
ADDR = First Location
VCC = 6.25 V
V
PP
= 12.75V
X = 0
Program one 100 µs Pulse
Increment X
X = 20 ?
Verify
Byte
Device
Failed
Fail
Pass
Pass
Last
Address
Increment ADDR
Fail
Yes
No
Pass
Device Passed
Verify
Byte
1st
VCC = VPP =5.5V
2nd V
CC
= VPP =4.5V
Device
Failed
Fail
FIGURE 1.
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64 are listed in Table
1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The V
PP
power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The V
CC
power supply must be at 6V during the three programming modes, and at 5V in the other three modes.
Read Mode
ACC
) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE , assuming that CE has been low and addresses have been stable for at least t
ACC
–
tOE. The sense amps are clocked for fast access time. VCC should
Standby Mode
The NMC27C64 has a standby mode which reduces the active power dissipation by 99%, from 55 mW to 0.55 mW. The NMC27C64 is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Output OR-Tying
Because NMC27C64s are usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommo­dates this use of multiple memory connections. The 2-line control function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recomended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a common connec­tion to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the NMC27C64.
The NMC27C64 is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.
For programming, CE should be kept TTL low at all times while V
PP
is kept at 12.75V. When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The NMC27C64 is programmed with the Fast Programming Algorithm shown in Figure 1. Each address is programmed with a series of 100 µs pulses until it verfies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 µs pulse. The NMC27C64 must not be programmed with a DC signal applied to the PGM input.
Programming multiple NMC27C64s in parallel with the same data can be easily accomplished due to the simplicity of the program­ming requirements. Like inputs of the paralleled NMC27C64s may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled NMC27C64s. If an application requires erasing and reprogramming, the NMC27C64Q UV erasable PROM in a win­dowed package should be used.
TABLE 1. Mode Selection
Pins CE OE PGM V
PP
V
CC
Outputs
Mode (20) (22) (27) (1) (28) (11–13, 15–19)
Read V
IL
V
IL
V
IH
5V 5V D
OUT
Standby V
IH
Don’t Care Don’t Care 5V 5V Hi-Z
Output Disable Don’t Care V
IH
V
IH
5V 5V Hi-Z
Program V
IL
V
IH
13V 6V D
IN
Program Verify V
IL
V
IL
V
IH
13V 6V D
OUT
Program Inhibit V
IH
Don’t Care Don’t Care 13V 6V Hi-Z
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Functional Description (Continued)
Program Inhibit
Programming multiple NMC27C64s in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel NMC27C64 may be common. A TTL low level program pulse applied to an NMC27C64’s PGM input with CE at VIL and VPP at 13.0V will program that NMC27C64. A TTL high level CE input inhibits the other NMC27C64s from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 13.0V. VPP must be at VCC, except during programming and program verify.
MANUFACTURER’S IDENTIFICATION CODE
The NMC27C64 has a manufacturer’s identification code to aid in programming. The code, shown in Table 2, is two bytes wide and is stored in a ROM configuration on the chip. It identifies the manufacturer and the device type. The code for the NMC27C64 is “8FC2”, where “8F” designates that it is made by Fairchild Semiconductor, and “C2” designates a 64k part.
The code is accessed by applying 12V ± 0.5V to address pin A9. Addresses A1–A8, A10–A12, CE, and OE are held at VIL. Address A0 is held at VIL for the manufacturer’s code, and at VIH for the device code. The code is read out on the 8 data pins. Proper code access is only guaranteed at 25°C ± 5°C.
The primary purpose of the manufacturer’s identification code is automatic programming control. When the device is inserted in a EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C64 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å – 4000Å range.
After programming, opaque labels should be placed over the NMC27C64’s window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.
The NMC27C64 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, compo­nents, and even system designs have been erroneously sus­pected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
CC
transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
TABLE 2. Manufacturer’s Identification Code
Pins A0 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code
V
IL
100011118F
Device Code V
IH
11000010C2
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NMC27C64 Rev. C
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex­pected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, T simshatsui East 2-18-6, Yushima, Bunkyo-ku
English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841
0.625
+0.025
-0.015
0.008-0.015
(0.229-0.381)
15.88
+0.635
-0.381
0.580
(14.73)
95° ±5°
0.600 - 0.620
(15.24 - 15.75)
0.030
(0.762)
Max
(
(
0.108 ±0.010
(2.540 ±0.254)
0.018 ±0.003
(0.457 ±0.076)
0.20
(0.508)
0.125-0.145
(3.175-3.583)
0.125-0.165
(3.175-4.191)
0.050
(1.270)
Typ
0.053 - 0.069
(1.346 - 1.753)
0.050 ±0.015
(1.270 ±0.381)
Min
88° 94°
Typ
1234
2827 26 25
1.393 - 1.420
(35.38 - 36.07)
0.510 ±0.005
(12.95 ±0.127)
0.062
(1.575)
Pin #1 IDENT
5246
23 22 2120 19 18 17 16
7 8 9 1011121314
15
RAD
Dual-In-Line Package (N)
Order Number NMC27C64N
Package Number N28B
1.260 MAX (32.00)
24
1
13
12
0.025 (0.64)
0.030-0.055 (0.76 - 1.4)
0.270 - 0.290 (6.88 - 7.39)
UV WINDOW
0.590-0.620
(15.03 - 15.79)
0.180
(4.59)
MAX
0.060-0.100
(1.53 - 2.55)
TYP
0.050-0.060 (1.27 - 1.53)
0.015-0.021
(0.38 - 0.53)
TYP
Glass Sealant
0.020 -0.070 (0.51 - 1.78)
TYP
0.10 (2.5) MAX
0.090-0.110 (2.29 - 2.80)
TYP
0.225 (5.73)
0.125 MIN (3.18)
TYP
90° - 100°
TYP
0.685
(17.40)
+0.025 (0.64)
-0.060 (-1.523)
0.008-0.015
(0.20 - 0.38)
TYP
0.514 - 0.526
(13.06 - 13.21)
R
R
TYP
TYP
MAX TYP
Dual-In-Line Package (Q)
Order Number NMC27C64Q
Package Number J28AQ
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