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NM95MS14
Datasheet
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Datasheet NM95MS14 Datasheet

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Page 1
NM95MS14 User’s Guide
The User’s Guide contains the description of certain internal registers and PnP resource data registers in the E2PROM. The internal registers are used by the chip for power-on configuration. The PnP resource data registers are for PnP resource allocation.
Power-On Configuration Load
Word Byte Purpose of the
Address Address 16-Bit Register
00 0000 I/O Decode Qualification Bits
01 0002 DMA Level Selection Bits
02 0004 Interrupt Level SelectionÐA
03 0006 Interrupt Level SelectionÐB
04 0008 Chip Select 0 Decode Size
05 000A Chip Select 1 Decode Size
06 000C Chip Select 2 Decode Size
07 000E Chip Select 3 Decode Size
08 0010 Reserved for Future Use
09 0012 Reserved for Future Use
0A 0014 Reserved for Future Use
0B 0016 Reserved for Future Use
0C 0018 Reserved for Future Use
0D 001A Reserved for Future Use
0E 001C Reserved for Future Use
0F 001E Reserved for Future Use
10 0020 Vendor ID
11 0022 Vendor ID
12 0024 Serial Number
13 0026 Serial Number
14 (LSB) 0028 LSBeChecksum of
(Vendor ID
a
Serial Num.)
14 (MSB) 0029 MSBeStart of Resource Data
Structure
is a registered trademark of National Semiconductor Corporation.
TRI-STATE
É
MICROWIRETMis a trademark of National Semiconductor Corporation.
Each of the above registers is now discussed in detail be­low.
I/O DECODE QUALIFICATION REGISTER
15–10 9–8 7–4 3 2 1 0
RFU MS RFU RWQ3 RWQ2 RWQ1 RWQ0
RWQk3:0l: Read, Write Qualify:ÐIf this bit is set to 0, then the I/O chip selects are qualified by IOWR in a write cycle and IORD in a read cycle. If 1, the I/O chip selects are derived from addresses only.
MS: Mode Select Bits. If these bits are set to ‘00’, then DMA mode is selected. When set to ‘01’ Extended Interrupt/ Chip-select expansion mode is selected.
RFU: Reserved for Future Use: Must be set to ‘0’.
DMA LEVEL SELECTION REGISTER
15–8 7–5 4–3 2–0
RFU ISA DRQ1 RFU ISA DRQ0
ISADRQk1:0l: These pins will be physically connected to ISA DRQ lines. This will allow the user to customize his choice of 2 out of 7 available ISADRQ channels on the bus. For example if ISA DRQ0 is connected to DRQ5 on the ISA bus then bits ‘2–0’ should be set as ‘101’ meaning ISADRQ0 is assigned to DRQ/DACK 5.
This register is valid only for DMA mode (MODE ‘00’). For Mode ‘01’ all of the bits of this register are Don’t Care.
RFU: Reserved for Future Use: Must be set to ‘0’.
INTERRUPT LEVEL SELECTION REGISTERÐA
15–12 11–8 7–4 3–0
IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0
INTERRUPT LEVEL SELECTION REGISTERÐB
15–12 11–8 7–4 3–0
IRQOUT7 IRQOUT6 IRQOUT5 IRQOUT4
IRQOUT[7:0]: These pins will be physically connected to the ISA IRQ lines on the bus as specified in the registers above. This will enable the user to customize his choice of 8 out of 11 available ISA IRQ channels. For example, if IRQOUT0 is assigned to IRQ7 on the ISA bus, then bits ‘3–0’ should be set as ‘0111’, meaning IRQOUT0 is as­signed to IRQ7. In DMA mode bits (8 – 15) of Interrupt Level Selection RegisterÐB are Don’t Care.
NM95MS14 User’s Guide
Page 2
Power-On Configuration Load (Continued)
k
l
CHIP SELECT DECODE SIZE REGISTER
15–8 7–0
RFU Chip Select Decode Size
Chip Select Decode Size: These bits function as masks in the chip select decode function and will set the size of the decode (from the base address) according to the selections as shown.
NM95MS14 User’s Guide
Chip Select
Decode Size Bits Decode Size
00000000 1 byte 00000001 2 bytes 00000011 4 bytes 00000111 8 bytes 00001111 16 bytes 00011111 32 bytes 00111111 64 bytes 01111111 128 bytes 11111111 256 bytes
3:0
RFU: Reserved for Future Use.
Vendor ID Registers: The lower address contains the least
significant word of the Vendor ID (as defined in the Plug & Play Standard) and the higher address contains the most significant word.
Serial Number Registers: The lower address contains the least significant word of the Serial number of the Card (as defined in the Plug & Play Standard) and the higher address contains the most significant word.
Checksum Register: This 8-bit quantity occupies the lower 8-bits of the word at address 0014 (Byte address 0028). This checksum is the LFSR checksum of the vendor ID and the Serial Number. Please refer to the PnP standard on how to compute this checksum.
Start of Resource Data structure: The resource data structure begins at the MSB of word address 0014 (Byte address 0029).
Page 3
Plug & Play Registers Implemented on the NM95MS14
TABLE A. Plug & Play Standard Registers
Name Port Definition
Set RDÐDATA Port 0x00 Writing to this location modifies the address of the port used for reading from the Plug &
Serial Isolation 0x01 A read to this register causes the Plug & Play cards in the
Config Control 0x02 Bit[2]ÐReset CSN to 0
Wake[CSN
Resource Data 0x04 A read from this address reads the next byte of resource information. The Status register
Status 0x05 Bit[0]when set indicates it is okay to read the next data byte from the Resource Data
Card Select Number 0x06 A write to this port sets a card’s CSN. The CSN is a value uniquely assigned to each ISA
Logical Device Number 0x07 Selects the current logical device. All reads and writes of memory, I/O, interrupt and
]
Address
Value
Play ISA cards. Bits[7:0]become I/O read port address bits[9:2]. Reads from this register are ignored.
bit of the boards ID. This process is fully described above. This register is read only.
Isolation
Bit[1]ÐReturn to the
Bit[0]ÐReset all logical devices and restore configuration registers to their power-up values.
A write to bit[0]of this register performs a reset function on all logical devices. This resets the contents of configuration registers to their default state. All card’s logical devices enter their default state and the CSN is preserved.
A write to bit[1]of this register causes all cards to enter the CSNs are preserved and logical devices are not affected.
A write to bit[2]of this register causes all cards to reset their CSN to zero.
This register is write-only. The values are not sticky, that is, hardware will automatically clear them and there is no need for software to clear the bits.
0x03 A write to this port will cause all cards that have a CSN that matches the write data[7:0
to go from the is zero or the byte-serial device is reset. This register is write-only.
must be polled until bit[0]is set before this register may be read. This register is read only.
register. This register is read-only.
card after the serial identification process so that each card may be individually selected during a Wake[CSN]command. This register is read/write.
DMA configuration information access the registers of the logical device written here. In addition, the I/O Range Check and Activate commands operate only on the selected logical device. This register is read/write. If a card has only 1 logical device, this location should be a read-only value of 0x00.
Wait for Key
Sleep
state to either the
Config
state if the write data is not zero. Additionally, the pointer to the
state
Isolation
state if the write data for this command
state to compare one
Wait for Key
state but all
NM95MS14 User’s Guide
]
Page 4
Plug & Play Registers Implemented on the NM95MS14 (Continued)
TABLE A-1. Plug and Play Logical Device Control Registers
Name Port Definition
Activate 0x30 For each logical device there is one activate register that controls whether
NM95MS14 User’s Guide
I/O Range Check 0x31 This register is used to perform a conflict check on the I/O port range
I/O Port Base Address Bits[15:8 Descriptor 0
I/O Port Base Address Bits[7:0 Descriptor 0
I/O Port Address Descriptors[1–6]0x62–0x6D I/O base addresses for I/O descriptors 1 – 6.
I/O Port Base Address Bits[15:8 Descriptor 7
I/O Port Base Address Bits[7:0 Descriptor 7
]
]
Address
Value
or not the logical device is active on the ISA bus. Bit[0], if set, activates the logical device. Bits[7:1]are reserved and must return 0 on reads. This is a read/write register. Before a logical device is activated, I/O range check must be disabled.
programmed for use by a logical device.
Bit[7:2]Reserved and must return 0 on reads.
Bit[1]Enable I/O Range check, if set then I/O Range Check is enabled. I/O range check is only valid when the logical device is inactive.
Bit[0], if set, forces the logical device to respond to I/O reads of the logical device’s assigned I/O range with a 0x55 when I/O range check is in operation. If clear, the logical device drives 0xAA. This register is read/ write.
]
]
0x60 Read/write value indicating the selected I/O lower limit address bits[15:8
for I/O descriptor 0. If a logical device indicates it only uses 10 bit decoding, then bits[15:10]do not need to be supported.
0x61 Read/write value indicating the selected I/O lower limit address bits[7:0
for I/O descriptor 0.
0x6E Read/write value indicating the selected I/O base address bits[15:8]for
I/O descriptor 3. If a logical device indicates it only uses 10 bit decoding, then bits[15:10]do not need to be supported.
0x6F Read/write value indicating the selected I/O base address bits[7:0]for
I/O descriptor 3.
]
]
TABLE A-2. Interrupt Configuration
Name
Interrupt Request Level Select 0 0x70 Read/write value indicating selected interrupt level. Bits[3:0]select which
Interrupt Request Type Select 0 0x71 Read/write value indicating which type of interrupt is used for the Request Level
Interrupt Request Level Select 1 0x72 Read/write value indicating selected interrupt level. Bits[3:0]select which
Interrupt Request Type Select 1 0x73 Read/write value indicating which type of interrupt is used for the Request Level
Register
Index
Definition
interrupt level is used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is not a valid interrupt selection and represents no interrupt selection.
selected above.
e
Bit[1]: Level, 1 Bit[0]: Type, 1
If a card only supports 1 type of interrupt, this register may be read-only.
interrupt level is used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is not a valid interrupt selection and represents no interrupt selection.
selected above.
Bit[1]: Level, 1 Bit[0]: Type, 1
high, 0elow
e
level, 0eedge
e
high, 0elow
e
level, 0eedge
Page 5
Plug & Play Registers Implemented on the NM95MS14 (Continued)
TABLE A-3. DMA Channel Configuration
Name
DMA Channel Select 0 0x74 Read/write value indicating selected DMA channels. Bits[2:0]select which DMA channel
DMA Channel Select 0 0x75 Read/write value indicating selected DMA channels. Bits[2:0]select which DMA channel
Register
Index
Definition
is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel is active.
is in use for DMA 1. Zero selects DMA channel 0, seven selects DMA channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel is active.
Programming Interface
TABLE A-4. Programming E2PROM Registers
Name
Status and Command Register 0xF0 Bit[1:0]ÐOP Code bits
Address Register 0xF1 Address Register[A0–A7
Data Register 0xF2 Data Byte[MSB
Data Register 0xF3 Data Byte[LSB
Register
Index
Definition
10ÐRead operation 01ÐWrite operation 11ÐErase operation
Bit[2]ÐGA (Go ahead bits)
If set to 1, the programming will continue
Bit[3]ÐStatus/Busy
Since EEPROM is a slow device, this bit is provided to show that EEPROM is still BSY and the previous data is getting programmed. The user program should poll this bit and should proceed only if this bit is 0. If it is set to 1, it means BSY.
Bit[6:4]ÐReserved, should be 0
Bit[7]ÐIt provides A8 of the address
[
A0–A7]is provided by Address Reg.
]
]
]
NM95MS14 User’s Guide
EEPROM PROGRAMMING METHOD
A total of 6k bits of EEPROM is available on-chip. Of this, 2k bits are dedicated for the Plug & Play Access and the 4k bits are available for access externally. For purposes of pro­gramming the contents of the EEPROM, the entire 6k bits are accessible via the ISA bus.
Specifically, the contents of the EEPROM may be altered by putting the device in the Config State (as defined in the Plug & Play Standard). Under this state, the following registers detaiIed above are accessible. The data to be programmed is loaded in registers at address 0xF3 and 0xF4 (LSB and
MSB respectively). The address to be programmed is load­ed in register at address 0xF1. Addressing 6k bits of memo­ry requires 9 bits of address. The ninth bit of address is provided through the register at address 0xF0.
Both read and write operations are possible. The opcodes are as indicated in the table. The actual operation does not begin until the Go Ahead (GA) bit is set. Programming a word takes approximately 10 ms. The status of the opera­tion can be poIIed by the status bit. This bit is set when the operation is in progress and will be reset when compIete.
Page 6
Programming Interface (Continued)
EEPROM CHARACTERISTICS (FOR EXTERNAL ACCESS)
Symbol Parameter Conditions Min Max Units
f
SK
t
SKH
t
SKL
t
NM95MS14 User’s Guide
t
t
t
t
t
t
t
t
t
t
SKS
CS
CSS
DH
DIS
DIH
PD1
PD0
SV
DF
WP
AVAILABILITY OF EXTRA 4k EEPROM
The extra 4k EEPROM built into NM95MS14 for the Functio­naI Iogic to be used for other purposes becomes available after the DO pin on the EEPROM MICROWIRE comes high. This DO pin is pulled Iow when the EEPROM is accessed internally by the Plug & Play Iogic.
LEGACY ISA SYSTEMS
The LEGACY system coIIectively refers to Older ISA cards or Systems that are not Plug & Play compatible (Mother­board BIOS being Non PnP compliant).
In a LEGACY system there can be two of the following situ­ations where NM95MS14 will be used.
a) NM95MS14 on a Non Bootable ISA ADD-ON Plug &
Play Card.
Under this situation, the card will be Powered ON inac­tive. Once the system is Booted, NM95MS14 can be configured by the O/S (Windows’95) or by the external PnP utiIities.
b) NM95MS14 on a Bootable ISA ADD-ON Plug & Play
Card.
Since the card cannot on its own come up active unless some PnP Software configures it, NM95MS14 cannot be used for a Bootable card on a Legacy system.
SK Clock Frequency 0 1 MHz
SK High Time 250 ns
SK Low Time 250 ns
SK Setup Time 50 ns
CS Low Time (min) 250 ns
CS Setup Time Relative to SK 50 ns
DO HoId Time Relative to SK 70 ns
DI Setup Time Relative to SK 100 ns
DI Hold Time Relative to SK 20 ns
Output Delay to ‘‘1’’ Relative to SK 500 ns
Output Delay to ‘‘0’’ Relative to SK 500 ns
CS to Status Valid Relative to SK 500 ns
CS to DO in TRI-STATEÉC
Write CycIe Time C
TM
port be-
e
V
S
IL
e
V
S
IL
100 ns
10 ms
Addendum
DMA LEVEL SELECTION REGISTER
15–8 7–6 5–3 2–0
RFU RFU ISADRQ1 ISADRQ0
ISADRQk1:0l: These pins will be physically connected to ISA DRQ Iines. This will allow the user to customize his choice of 2 out of 7 available ISADRQ channels on the bus. For example if ISADRQ0 is connected to DRQ5 on the ISA bus then bits ‘2–0’ should be set as ‘101’ meaning ISADRQ0 is assigned to DRQ/DACK 5.
RFU: Reserved for Future Use: Must be set to ‘0’.
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