Page 1
March 1999
NM34W02
2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules (PC100 Compliant)
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
General Description
The NM34W02 is 2048 bits of CMOS non-volatile electrically
erasable memory. This device is specifically designed to support
Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA)
lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical characteristics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
The first 128 bytes of the memory of the NM34W02 can be
permanently Write Protected by writing to the "WRITE PROTECT"
Register. Write Protect implementation details are described
under the section titled Addressing the WP Register. In addition,
like the NM24Wxx product family, the entire memory array can be
write-protected through "WP" pin.
The NM34W02 is available in a JEDEC standard TSSOP package
for low profile memory modules for systems requiring efficient
space utilization such as in a notebook computer. Two options are
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
Block Diagram
V
CC
V
SS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
Write Protect
Register
CONTROL
LOGIC
LOAD INC
WORD
ADDRESS
COUNTER
R/W
Device Address Bits
D
IN
Features
■ PC100 Compliant
■ Extended Operating Voltage: 2.7V-5.5V
■ Software Write-Protection for first 128 bytes
■ Hardware Write-Protection for entire memory array
■ 200 µA active current typical
– 1.0 µA standby current typical (L)
– 0.1 µA standby current typical (LZ)
■ IIC compatible interface
– Provides bidirectional data transfer protocol
■ Sixteen byte page write mode
– Minimizes total write time per byte
■ Self timed write cycle
- Typical write cycle time of 6ms
■ Endurance: 1,000,000 data changes
■ Data retention greater than 40 years
■ Packages available: 8-pin TSSOP and 8-pin SO
■ Temperature Ranges: Commercial and Extended
0/1/2/3
4
TIMING &CONTROL
16
H.V. GENERATION
E2PROM
ARRAY
16 x 16 x 8
16
YDEC
8
DATA REGISTER
D
OUT
START CYCLE
XDEC
4
CK
© 1999 Fairchild Semiconductor Corporation
NM34W02 Rev. C.2
DS500078-1
1
www.fairchildsemi.com
Page 2
Connection Diagram
SO (M8) and TSSOP (MT8) Package
A0
A1
1
2
V
8
CC
WP
7
NM34W02
A2
3
V
SS
4
SCL
6
SDA
5
DS500078-2
Top View
See Package Number
M08A and MTC08
Pin Names
A0,A1,A2 Device Address Inputs
V
SS
SDA Data I/O
SCL Clock Input
WP Write Protect
V
CC
Ground
Power Supply
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Ordering Information
NM 34 W 02 LZ E XX Letter Description
Package M8 8-Pin SO8
Temp. Range None 0 to 70°C
Voltage Operating Range Blank 4.5V to 5.5V
Density 02 2K
Interface 34 IIC
MT8 8-Pin TSSOP
E -40 to +85°C
L 2.7V to 4.5V
LZ 2.7V to 4.5V and
<1µA Standby Current
W Full Array Write Protect
NM Fairchild Non-Volatile
Memory
NM34W02 Rev. C.2
2
www.fairchildsemi.com
Page 3
Product Specifications
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Absolute Maximum Ratings
Ambient Storage Temperature –65°C to +150°C
All Input or Output Voltages
with Respect to Ground 6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds) +300°C
ESD Rating 2000V min.
Operating Conditions
Ambient Operating Temperature
NM34W02 0°C to +70°C
NM34W02E -40°C to +85°C
Positive Power Supply
NM34W02 4.5V to 5.5V
NM34W02L 2.7V to 4.5V
NM34W02LZ 2.7V to 4.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Limits Units
Min Typ Max
(Note 1)
I
V
V
CCA
I
SB
I
LI
I
LO
V
OL
IL
IH
Active Power Supply Current f
Standby Current VIN = GND or V
Input Leakage Current VIN = GND to V
Output Leakage Current V
= 100 kHz 0.2 1.0 mA
SCL
10 50 µA
0.1 1 µA
0.1 1 µA
= GND to V
OUT
CC
CC
CC
Input Low Voltage –0.3 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage I
= 3 mA 0.4 V
OL
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Limits Units
Min Typ Max
(Note 1)
I
CCA
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Capacitance T
Active Power Supply Current f
Standby Current for L VIN = GND or V
Standby Current for LZ VIN = GND or V
Input Leakage Current VIN = GND to V
Output Leakage Current V
Input Low Voltage –0.3 V
= 100 kHz 0.2 1.0 mA
SCL
110µA
0.1 1 µA
0.1 1 µA
0.1 1 µA
x 0.3 V
CC
= GND to V
OUT
CC
CC
CC
CC
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage IOL = 3 mA 0.4 V
= +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
A
Symbol Test Conditions Max Units
C
I/O
C
IN
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
Input/Output Capacitance (SDA) V
= 0V 8 pF
I/O
Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF
NM34W02 Rev. C.2
3
www.fairchildsemi.com
Page 4
AC Conditions of Test
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels VCC x 0.5
Output Load 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol Parameter 100 KHz 400 KHz Units
Min Max Min Max
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3) - NM34W02L, NM34W02LZ 15 15
SCL Clock Frequency 100 400 KHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
100 50 ns
Pulse width)
SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs
Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start
Start Condition Hold Time 4.0 0.6 µs
Clock Low Period 4.7 1.5 µs
Clock High Period 4.0 0.6 µs
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
Data in Hold Time 0 0 ns
Data in Setup Time 250 100 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4.7 0.6 µs
Data Out Hold Time 300 50 ns
Write Cycle Time - NM34W02 10 10 ms
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM34W02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
4
NM34W02 Rev. C.2
www.fairchildsemi.com
Page 5
Bus Timing
SCL
SDA
SDA
OUT
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
t
LOW
t
R
t
t
SU:DAT
t
DH
SU:STO
t
BUF
DS500078-5
t
F
t
t
LOW
t
SU:STA
IN
t
HD:STA
HIGH
t
HD:DAT
t
AA
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a device type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010. Also refer the Addressing the WP Register section.
As shown below, although the EEPROMs on the IIC bus may be
configured in any manner required, the total memory addressed
can not exceed 16K (16,384 bits) on the Standard IIC. EEPROM
memory address programming is controlled by 2 methods:
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to VCC or VSS. All
unused pins must be grounded (tied to VSS).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
Example of 16K of Memory on 2-Wire Bus
DEFINITIONS
BYTE 8 bits of data
PAGE 16 sequential addresses (one byte
PAGE BLOCK 2,048 (2K) bits organized into 16
MASTER Any IIC device CONTROLLING the
SLAVE Device being controlled (EEPROMs
TRANSMITTER Device currently SENDING data on
RECEIVER Device currently receiving data on the
each) that may be programmed
during a 'Page Write' programming
cycle
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
transfer of data (such as a microprocessor)
are always considered Slaves)
the bus (may be either a Master or
Slave).
bus (Master or Slave)
V
CC
V
CC
SDA
SCL
Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
V
CC
NM34C02L
A0 A1 A2 V
To V
or V
CC
SS
SS
V
CC
NM24C02
A0 A1 A2 V
To V
or V
CC
SS
SS
5
NM34W02 Rev. C.2
V
CC
NM24C04
A0 A1 A2 V
To V
or V
CC
SS
SS
V
CC
NM24C08
A0 A1 A2 V
To V
or V
CC
SS
SS
DS500078-6
www.fairchildsemi.com
Page 6
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Device Address Pins
A0 A1 A2 Page Blocks
NM34W02 ADR ADR ADR 2048 Bits 1
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or V
to configure the EEPROM chip address. Table A shows the active
pins across the NM34W02 device family.
Table 1.
Device A0 A1 A2 Effects of Addresses
NM34W02 ADR ADR ADR 8 devices max.
SS
Device Operation
The NM34W02 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM34W02 will be considered a slave
in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to
Figures 1
and
2.
Memory Size
Number of
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The NM34W02
continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has
been met.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM34W02 to place the device in the
standby power mode.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to
Figure 3.
The NM34W02 device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
the device and a write operation have been selected, the NM34W02
will respond with an acknowledge after the receipt of each
subsequent eight bit byte.
In the Read mode the NM34W02 slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
NM34W02 Rev. C.2
6
www.fairchildsemi.com
Page 7
Write Cycle Timing
SCL
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
SDA
SCL
SDA
SCL
SDA
8th BIT ACK
WORD n
STOP
CONDITION
DATA STABLE
DATA
CHANGE
Data Validity (Figure 1).
START
CONDITION
Start and Stop Definition (Figure 2).
t
WR
START
CONDITION
DS500078-7
DS500078-8
STOP
CONDITION
DS500078-9
SCL FROM
MASTER
DATA OUTPUT
TRANSMITTER
DATA OUTPUT
FROM
FROM
RECEIVER
START
Acknowledge Responses from Receiver (Figure 3).
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (
is fixed as 1010 for all EEPROM devices.
NM34W02 Rev. C.2
see Figure 4)
189
ACKNOWLEDGE
DS500078-10
All IIC EEPROMs use an internal protocol that defines a PAGE
. This
BLOCK size of 2K bits (for Byte addresses 00 through FF).
7
www.fairchildsemi.com
Page 8
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Device Addressing (Continued)
Device Type
Identifier
1 0 1 0 A2 A1 A0 R/W (LSB)
NM34W02
Slave Addresses (Figure 4).
Refer to the following table for Slave Address string details:
Device A0 A1 A2 Page Page Block
NM34W02 A A A 1 (2K) (None)
Device
Address
DS500078-11
Blocks Addresses
Write Operations
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the NM34W02 recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address
to be transmitted over the SDA line. If the transmitted slave
address matches an address of one of the devices, the designated
slave pulls the line LOW with an acknowledge signal and awaits
further transmissions.
Byte Write
For a write operation a second address field is required which is
a byte address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page block of memory.
Upon receipt of the byte address the NM34W02 responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the NM34W02
begins the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the NM34W02 inputs are
disabled, and the device will not respond to any requests from the
master. Refer to
transfer sequence.
Page Write
The NM34W02 is capable of a sixteen byte page write operation.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte is
transferred, the master can transmit up to fifteen more bytes. After
the receipt of each byte, the NM34W02 will respond with an
acknowledge.
After the receipt of each byte, the internal address counter
increments to the next address and the next SDA data is accepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will 'roll over'
Figure 5
for the address, acknowledge and data
and the previously written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to
edge, and data transfer sequence.
Figure 6
for the address, acknowl-
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation the NM34W02 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the NM34W02 is still busy with the write operation no ACK will
be returned. If the NM34W02 has completed the write operation
an ACK will be returned and the host can then proceed with the
next read or write operation.
Software Write Protect
Software write protection on the NM34W02 protects the first 128
bytes of the EEPROM memory. Software write protection is
implemented through a seperate register called the WRITE PROTECT (WP) Register and writing to this WP register permanently
WRITE protects the memory. This WP register is a "one-time-
only-write" register. Once this register is written, it cannot be
erased. After the first WRITE to this register, all future access'
to this register are ignored as if an invalid IIC cycle occured.
To write protect, the user must perform a byte write to the WP
register. This will permanently disable programming to the first
128 bytes of memory.
Addressing the WP Register
Addressing the WP register is very similar to accessing any
memory array with the following difference:
Instead of the conventional "1010" IIC device address, the unused
IIC device address "0110" is used to access just the WP register.
Device address "1010" will be used for all the typical memory array
access. With this difference in place, accessing the WP register is
same as a typical IIC byte write cycle as described under "Write
Operations" section. All timing information and waveform details
remain the same. The "Byte Address" and the "Data" fields of the
Byte write cycle serve as place holders and can be of any value
(Don't Care). Refer to
Figure 7
.
Hardware Write Protect
Programming of the memory will not take place if the WP pin of the
NM34W02 is connected to VCC, regardless of whether the software write protect register has been implemented or not. The
NM34W02 will accept slave and word addresses; but if the
memory accessed is write protected by the WP pin, the NM34W02
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted. (Note: if the WP pin is set to VCC,
it will prevent the software write protect register from being
written.)
NM34W02 Rev. C.2
8
www.fairchildsemi.com
Page 9
Write Protect Scheme (Continued)
S
T
A
R
T
A
C
K
SLAVE
ADDRESS
Bus Activity:
Master
SDA Line
S
T
A
R
T
Bus Activity:
Master
SDA Line
SLAVE
ADDRESS
WORD
ADDRESS
A
C
K
Byte Write (Figure 5).
A
C
K
Page Write (Figure 6).
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
S
T
DATA
A
C
K
DATA n + 1DATA nBYTE ADDRESS (n)
A
C
K
O
P
A
C
K
DS500078-15
S
DATA n + 15
A
C
K
T
O
P
A
C
K
DS500078-16
S
T
SLAVE
Bus Activity:
Master
SDA Line
Bus Activity:
A
ADDRESS
R
T
DEVICE
ADDRESS
A
C
K
WP Register Write (Figure 7).
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
CURRENT ADDRESS READ
Internally the NM34W02 contains an address counter that maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
NM34W02 issues an acknowledge and transmits the data byte.
The master will not acknowledge the transfer but does generate
a stop condition, and therefore the NM34W02 discontinues transmission. Refer to
edge and data transfer.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address, R/W bit set to zero, and then the word address to
Figure 8
for the sequence of address, acknowl-
S
BYTE
ADDRESS
DATA
A
C
DON'T CAREDON'T CARE
K
T
O
P
A
C
K
DS500078-17
be read. After the slave word address acknowledge, the master
immediately reissues the start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowledge from the NM34W02 and then by the eight bit word. The
master will not acknowledge the transfer but does generate the
stop condition, and therefore the NM34W02 discontinues transmission. Refer to
Figure 9
for the address, acknowledge and data
transfer sequence.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM34W02 continues to output data for each acknowledge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter 'rolls over' and the
NM34W02 continues to output data for each acknowledge received. Refer to
transfer sequence.
Figure 10
for the address, acknowledge, and data
NM34W02 Rev. C.2
9
www.fairchildsemi.com
Page 10
Current Address Read (Figure 8)
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Bus Activity:
Master
SDA Line
Random Read (Figure 9)
S
T
SLAVE
Bus Activity:
Master
A
R
T
ADDRESS
SDA Line
Sequential Read (Figure 10)
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
A
C
K
A
C
K
S
T
A
R
T
DATA
SLAVE
ADDRESS
DS500078-18
S
T
O
P
A
C
K
DATA n
DS500078-19
Bus Activity:
Master
SDA Line
SLAVE
ADDRESS
A
C
K
A
C
K
Typical System Configuration (Figure 11)
SDA
SCL
Master
Transmitter/
Receiver
Note: Due to open drain configuration of SDA, a bus-level resistor is called for
(Typical value = 4.7Ω)
Slave
Receiver
Transmitter/
Slave
Receiver
A
C
K
DATA n + 2DATA n +1DATA n
Master
Transmitter
A
C
K
Master
Transmitter/
Receiver
DATA n + x
V
S
T
O
P
DS500078-20
CC
DS500078-21
NM34W02 Rev. C.2
10
www.fairchildsemi.com
Page 11
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8765
0.228 - 0.244
(5.791 - 6.198)
1234
Lead #1
IDENT
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
0.010 - 0.020
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
x 45°
0.150 - 0.157
(3.810 - 3.988)
0.04
(0.102)
All lead tips
8° Max, Typ.
All leads
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
0.014
(0.356)
8-Pin Molded Small Outline Package (M8)
Order Number NM34W02LM8/LZM8
Package Number M08A
0.050
(1.270)
Typ
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014 - 0.020
(0.356 - 0.508)
Typ.
NM34W02 Rev. C.2
11
www.fairchildsemi.com
Page 12
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
85
0.246 - 0.256
(6.25 - 6.5)
0.123 - 0.128
(3.13 - 3.30)
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
14
Pin #1 IDENT
0.169 - 0.177
(4.30 - 4.50)
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
DETAIL A
Typ. Scale: 40X
(1.78) Typ
(0.42) Typ
Land pattern recommendation
See detail A
0°-8°
0.020 - 0.028
(0.50 - 0.70)
Seating
(4.16) Typ
(0.65) Typ
plane
(7.72) Typ
0.0035 - 0.0079
Gage
plane
0.0075 - 0.0098
(0.19 - 0.25)
NM34W02 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Order Number NM34W02LMT8/LZMT8
Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor
Americas Europe Hong Kong Japan Ltd.
Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku
English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan
Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840
Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
12
NM34W02 Rev. C.2
www.fairchildsemi.com
Loading...