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查询NM27P512供应商
NM27P512
524,288-Bit (64K x 8) Processor Oriented
CMOS EPROM
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM
December 1993
General Description
The NM27P512 is a 512K Processor Oriented EPROM configured as 64k x 8. It’s designed to simplify microprocessor
interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the specification improvements are taken advantage
of in the system design. The NM27P512 is implemented in
National’s advanced CMOS EPROM process to provide excellent reliability and access times as fast as 120 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P512 remains compatible with industry standard
JEDEC pinout EPROMs. The maximum specification for output turn-off time has been reduced, eliminating the need for
wait states at the end of a read cycle. Also, the minimum
specification for output hold time has been increased, eliminating the need for external circuitry to hold the data.
Block Diagram
Features
Y
Fast output turn off to eliminate wait states
Y
Extended data hold time for microprocessor
compatibility
Y
High performance CMOS
Ð 120 ns access time
Y
JEDEC standard pin configuration
Y
Manufacturer’s identification code
TL/D/11365– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
NSC800
is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/D/11365
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Connection Diagrams
27C080 27C040 27C020 27C010 27C256
A19XX/VPPXX/VPPXX/V
A16A16A16A
A15A15A15A15V
A12A12A12A12A
A7A7A7A7A
A6A6A6A6A
A5A5A5A5A
A4A4A4A4A
A3A3A3A3A
A2A2A2A2A
A1A1A1A1A
A0A0A0A0A
O0O0O0O0O
O1O1O1O1O
O2O2O2O2O
GND GND GND GND GND
PP
16
PP
12
7
6
5
4
3
2
1
0
0
1
2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P512 pins.
Commercial Temp Range (0§Ctoa70§C)
Parameter/Order Number Access Time (ns)*
NM27P512 Q, N, V 120 120
NM27P512 Q, N, V 150 150
NM27P512 Q, N, V 200 200
Military Temp Range (b55§Ctoa125§C)
Parameter/Order Number Access Time (ns)*
NM27P512 QM 200 200
DIP
NM27P512
27C256 27C010 27C020 27C040 27C080
TL/D/11365– 2
V
XX/PGM XX/PGM A
V
CC
A
A
A
A
CE/PGM CE CE CE/PGM CE/PGM
A
14
A
13
A
8
A
9
A
11
OE OE OE OE OE/
A
10
O
7
O
6
O
5
O
4
O
3
CC
XX A
14
13
A
8
A
9
11
10
O
7
O
6
O
5
O
4
O
3
V
A
A
A
A
V
CC
A
17
A
14
A
13
A
8
A
9
A
11
A
10
O
7
O
6
O
5
O
4
O
3
V
CC
18
17
14
13
A
A
11
10
O
O
O
O
O
CC
A
18
A
17
A
14
A
13
A
8
9
7
6
5
4
3
8
A
9
A
11
VPP
A
10
O
7
O
6
O
5
O
4
O
3
Extended Temp Range (b40§Ctoa85§C)
Parameter/Order Number Access Time (ns)*
NM27P512 QE, NE, VE 120 120
NM27P512 QE, NE, VE 150 150
NM27P512 QE, NE, VE 200 200
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
*All versions are guaranteed to function for slower speeds.
Package Types: NM27P512 Q, N, V XXX
e
Q
Quartz-Windowed Ceramic DIP Package
e
N
Plastic OTP DIP Package
e
V
PLCC Package
All packages conform to the JEDEC standard.
#
Pin Names
A0–A15 Addresses
CE Chip Enable
OE Output Enable
O0–O7 Outputs
PGM Program
XX Don’t Care (During Read)
PLCC
TL/D/11365– 3
2
Page 3
Absolute Maximum Ratings (Note 1)
V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground
VPPand A9 with Respect to Ground
b
65§Ctoa150§C
b
0.6V toa7V
b
0.7V toa14V
Supply Voltage with
CC
Respect to Ground
ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground V
b
a
1.0V to GNDb0.6V
CC
0.6V toa7V
l
2000V
Operating Range
Range Temperature V
Comm’l 0§Ctoa70§C
Industrial
Military
b
40§Ctoa85§C
b
55§Ctoa125§C
CC
a
5V
a
5V
a
5V
Tolerance
g
10%
g
10%
g
10%
Read Operation
DC Electrical Characteristics
Symbol Parameter Test Conditions Min Max Units
V
IL
V
IH
VOLOutput Low Voltage I
V
OH
(10)
I
SB1
I
SB2
ICCVCCActive Current CEeOEeVIL,f
I
PP
V
PP
I
LI
ILOOutput Leakage Current V
Input Low Level
Input High Level 2.0 V
e
2.1 mA 0.4 V
OL
Output High Voltage I
VCCStandby Current (CMOS) CEeV
VCCStandby Current CEeV
VPPSupply Current V
eb
2.5 mA 3.5 V
OH
g
0.3V 100 mA
CC
IH
e
I/O
e
0mA
e
V
PP
CC
5 MHz
VPPRead Voltage V
Input Load Current V
IN
OUT
e
5.5V or GND
e
5.5V or GND
b
0.5 08 V
a
1V
CC
1mA
40 mA
10 m A
b
0.7 V
CC
b
11mA
b
10 10 m A
CC
V
AC Electrical Characteristics
Symbol Parameter
t
ACC
t
CE
t
OE
t
DF
t
CF
t
OH
(2)
(2)
(2)
Address to Output Delay 120 150 200
CE to Output Delay 120 150 200
OE to Output Delay 50 50 50
Output Disable to Output Float 25 25 25
Chip Disable to Output Float 30 30 30
Output Hold from Addresses, CE
, Whichever Occurred First
or OE
120 150 200
Min Max Min Max Min Max
777
3
Units
ns
Page 4
Capacitance T
ea
25§C, fe1 MHz (Note 2)
A
Symbol Parameter Conditions Typ Max Units
C
IN1
C
OUT
C
IN2
Input Capacitance V
except OE
/V
PP
Output Capacitance V
OE/VPPInput V
Capacitance
AC Test Conditions
Output Load 1 TTL Gate and
Input Rise and Fall Times
Input Pulse Levels 0.45V to 2.4V
e
C
100 pF (Note 8)
L
s
5ns
AC Waveforms (Notes 6, 7)
e
0V
IN
OUT
IN
e
e
0V
612pF
0V 9 12 pF
20 25 pF
Timing Measurement Reference Level (Note 9)
Inputs 0.8V and 2V
Outputs 0.8V and 2V
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE
Note 4: The t
Note 5: TRI-STATE may be attained using OE
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on
every device between V
Note 7: The outputs must be restricted to V
Note 8: 1 TTL Gate: I
Note 9: Inputs and outputs can undershoot to
Note 10: CMOS inputs; V
may be delayed up to t
and tCFcompare level is determined as follows:
DF
High to TRI-STATE, the measured V
Low to TRI-STATE, the measured V
OL
: 100 pF includes fixture capacitance.
C
L
CC
e
IL
and GND.
1.6 mA, I
e
ACC–tOE
GNDg0.3V, V
after the falling edge of CE without impacting t
(DC)b0.10V;
OH1
(DC)a0.10V.
OL1
or CE.
a
1.0V to avoid latch-up and device damage.
CC
eb
400 mA.
OH
b
2.0V for 20 ns Max.
e
g
V
IH
0.3V.
CC
ACC
.
TL/D/11365– 4
4
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Programming Characteristics (Notes 1 and 2)
Symbol Parameter Conditions Min Typ Max Units
t
AS
t
OES
t
DS
t
VCS
t
AH
t
DH
t
CF
t
PW
t
OEH
t
DV
t
PRT
t
VR
I
PP
I
CC
T
R
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Address Setup Time 1 ms
OE Setup Time 1 ms
Data Setup Time 1 ms
VCCSetup Time 1 ms
Address Hold Time 0 ms
Data Hold Time 1 ms
Chip Enable to Output Float Delay OEeV
IL
060ns
Program Pulse Width 95 100 105 ms
OE Hold Time 1 ms
Data Valid from CE OEeV
OE Pulse Rise Time
during Programming
IL
50 ns
250 ns
VPPRecovery Time 1 ms
VPPSupply Current during CEeV
Programming Pulse OE
IL
e
V
PP
30 mA
VCCSupply Current 50 mA
Temperature Ambient 20 25 30
Power Supply Voltage 6 6.25 6.5 V
Programming Supply Voltage 12.5 12.75 13 V
Input Rise, Fall Time 5 ns
Input Low Voltage 0 0.45 V
Input High Voltage 2.4 4 V
Input Timing Reference Voltage 0.8 2 V
Output Timing Reference Voltage 0.8 2 V
C
§
Programming Waveforms
Note 1: National’s standard product warranty applies to devices programmed to specifications described herein.
Note 2: V
board with voltage applied to V
Note 3: The maximum absolute allowable voltage which may be applied to the V
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VCCto GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings.
must be applied simultaneously or before VPPand removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a
CC
PP
or VCC.
pin during programming is 14V. Care must be taken when switching the V
PP
5
TL/D/11365– 5
PP
Page 6
Fast Programming Algorithm Flow Chart
FIGURE 1
TL/D/11365– 6
6
Page 7
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are V
OE/V
. The OE/VPPpower supply must be at 12.75V dur-
PP
ing the three programming modes, and must be at 5V in the
other three modes. The V
during the three programming modes, and at 5V in the other
power supply must be at 6.25V
CC
three modes.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OE/V
output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (t
the delay from CE to output (t
outputs t
has been low and addresses have been stable for at least
t
ACC–tOE
after the falling edge of OE, assuming that CE
OE
.
). Data is available at the
CE
ACC
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 385 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).
Output OR-Typing
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary
device selecting function, while OE/V
mon connection to all devices in the array and connected to
be made a com-
PP
the READ line from the system control bus.
and
CC
)isthe
PP
) is equal to
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 22 (OE/V
the EPROM.
) will damage
PP
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively programming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
The EPROM is in the programming mode when the OE/V
is at 12.75V. It is required that at least a 0.1 mF capacitor be
placed across V
transients which may damage the device. The data to be
to ground to suppress spurious voltage
CC
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed.
The EPROM is programmed with the Fast Programming Algorithm shown in
Figure 1
. Each Address is programmed
with a series of 100 ms pulses until it verifies good, up to a
maximum of 25 pulses. Most memory cells will program with
a single 100 ms pulse.
The EPROM must not be programmed with a DC signal applied to the CE/PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OE/V
be common. A TTL low level program pulse applied to an
EPROM’s CE/PGM input with OE/V
gram that EPROM. A TTL high level CE/PGM input inhibits
) of the parallel EPROMs may
PP
at 12.75V will pro-
PP
the other EPROMs from being programmed.
PP
7
Page 8
Functional Description (Continued)
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OE/V
should be verified T
after the falling edge of CE.
DV
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer’s Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P512 is ‘‘8F85’’, where ‘‘8F’’ designates that
it is made by National Semiconductor, and ‘‘85’’ designates
a 512K part.
The code is accessed by applying 12V
pin A9. Addresses A1–A8, A10 –A16, and all control pins
are held at V
facturer’s code, and held at V
. Address pin A0 is held at VILfor the manu-
IL
code is read on the eight data pins, O
access is only guaranteed at 25
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ð –4000Ð range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wave-
and CE at VIL. Data
PP
g
0.5V to address
for the device code. The
IH
Cg5§C.
§
. Proper code
0–O7
length of 2537Ð. The integrated dose (i.e., UV intensity
exposure time) for erasure should be minimum of
15W-sec/cm
2
.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum EPROM erasure time for various light
intensities.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, I
has three segments that are of interest to the system de-
CC
signer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated V
peaks can be suppressed by properly selected decoupling
transient voltage
CC
capacitors. It is recommended that at least a 0.1 mF ceramic
capacitor be used on every device between V
This should be a high frequency capacitor of low inherent
and GND.
CC
inductance. In addition, at least a 4.7 mF bulk electrolytic
capacitor should be used between V
eight devices. The bulk capacitor should be located near
and GND for each
CC
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
c
,
8
Page 9
Mode Selection
The modes of operation of the NM27P512 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels excepts for V
Pins
Mode
Read V
Output Disable X
Standby V
Programming V
Program Verify V
Program Inhibit V
Note 1: X can be VILor VIH.
Pins
Manufacturer Code VIL12V100011118F
Device Code VIH12V1000010185
and A9 for device signature.
PP
TABLE I. Mode Selection
CE
/PGM OE/V
IL
(Note 1)
IH
IL
IL
IH
PP
V
IL
V
IH
X 5.0V High Z
12.75V 6.25V D
V
IL
12.75V 6.25V High Z
V
CC
5.0V D
5.0V High Z
6.25V D
TABLE II. Manufacturer’s Identification Code
A0 A9 07 06 05 04 03 02 01 00 Hex
(10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data
Outputs
OUT
IN
OUT
9
Page 10
10
Page 11
Physical Dimensions inches (millimeters)
UV Window Cavity Dual-In-Line Cerdip Package (Q)
28-Lead Plastic One-Time-Programmable Dual-In-Line
Order Number NM27P512Q
NS Package Number J28CQ
Order Number NM27P512N
NS Package Number N28B
11
Page 12
Physical Dimensions inches (millimeters) (Continued)
32-Lead Plastic Leaded Chip Carrier (PLCC)
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM
Order Number NM27P512V
NS Package Number VA32A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: [email protected] Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
a
49) 0-180-532 78 32 Hong Kong
a
49) 0-180-532 93 58 Tel: (852) 2737-1600
a
49) 0-180-534 16 80 Fax: (852) 2736-9960
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