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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
NM27LV210
1,048,576-Bit (64K x 16) Low Voltage EPROM
General Description
The NM27LV210 is a high performance Low Voltage Electrical
Programmable read only memory. It is manufactured using
Fairchild’s latest EPROM technology. This technology allows the
part to operate at high speeds.
This Low Voltage and Low Power EPROM is designed with power
sensitive hand held and portable battery products in mind. This
allows for code storage of firmware for applications like notebook
computers, palm top computers, cellular phones, and HDD.
The NM27LV210 is one member of Fairchild’s growing Low
Voltage product family.
Block Diagram
July 1998
Features
■ 3.0V to 3.6V operation
■ 200 ns, 250 ns maximum access time
■ Low current operation
—20mA ICC active current @ 5 MHz
—50µA I
CC
standby current @ 5 MHz
■ Ultra low power operation
—60 µA standby power @ 3.3V
—50 mW active power @ 3.3V
■ Surface mount package option
—44-Pin PLCC
DS011376-1
© 1998 Fairchild Semiconductor Corporation
V
cc
GND
V
pp
OE
PGM
Output Enable
Chip Enable, and
Program Logic
Y
Decoder
X
Decoder
Output
Buffers
1,048,576-Bit
Cell Matrix
A
0 - A15
Address
Inputs
Data Outputs O
0 - O15
CE
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Connection Diagrams
PLCC Pin Configuration
Top View
Commercial Temperature Range
(0°C to +70°C) VCC = 3.3V ± 0.3
Parameter/Order Number Access Time (ns)
NM27LV210 V 200 200
NM27LV210 V 250 250
Pin Names
A0–A15 Addresses
CE Chip Enable
OE Output Enable
O0–O15 Outputs
PGM Program
XX Don’t Care (During Read)
NC No Connect
V
PP
Programming Voltage
Extended Temperature Range
(-40°C to +85°C) VCC = 3.3V ±0.3
Parameter/Order Number Access Time (ns)
NM27LV210 VE 250 250
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.
• Consult the FSC representative for newly released products/
packages.
O
12
O
11
O
10
O
9
O
8
GND
NC
O
7
O
6
O
5
O
4
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
O13O14O15XX/VPPNC
NC
A15A
14
O3O2O1O
0
OE
NC
A
0A1A2A3A4
1
23456
7
8
9
10
11
12
13
14
15
16
17
4041424344
38
37
36
35
34
33
32
31
30
2221201918 282726252423
29
39
CE
VCCXX/PGM
O
12
O
11
O
10
O
9
O
8
GND
NC
O
7
O
6
O
5
O
4
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
O13O14O15XX/VPPNC
NC
A15A
14
O3O2O1O
0
OE
NC
A
0A1A2A3A4
39
4041424344
1
2
3
4
5
6
7
8
9
10
11
3435363738
32
31
30
29
28
27
26
25
24
1615141312 222120191817
23
33
CE
VCCXX/PGM
DS011376-7
DS011376-3
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Absolute Maximum Ratings (Note 2)
Storage Temperature -65°C to +150°C
All Input Voltages except A9 with
Respect to Ground (Note 12) -0.6V to +7V
VPP and A9 with Respect to Ground -0.6V to +14V
VCC Supply Voltage with
Respect to Ground -0.6V to +7V
ESD Protection >2000V
All Output Voltages with
Respect to Ground (Note 11) VCC + 1.0V to GND - 0.6V
Operating Range
Range Temperature V
CC
Tolerance
Commercial 0°C to +70°C 3.3 ±0.3
Extended -40°C to +85°C 3.3 ±0.3
DC Read Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter Test Conditions Min Max Units
V
IL
Input Low Level -0.3 0.7 V
V
IH
Input High Level 2.0 VCC + 0.3 V
V
OL1
Output Low Voltage (TTL) 0.4 V
V
OH1
Output High Voltage (TTL) 2.4 V
V
OL2
Output Low Voltage (CMOS) 0.2 V
V
OH2
Output High Voltage (CMOS) VCC - 0.3 V
I
SB1
VCC Standby Current (TTL) CE = V
IH
150 µA
I
SB2
VCC Standby Current (CMOS) CE = VCC ±0.3V 50 µA
I
CC
VCC Active Current CE = OE = VIL, f = 5 MHz 20 mA
I/O = 0 µA
I
PP
VPP Supply Current VPP = V
CC
10 µA
I
LI
Input Load Current VIN = 3.3 or GND -1 1 µA
I
LO
Output Leakage Current V
OUT
= 3.3V or GND -1 10 µA
AC Read Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter 200 250 Units
Min Max Min Max
t
ACC
Address to Output Delay 200 250
t
CE
CE to Output Delay 200 250
t
OE
OE to Output Delay 70 75
t
DF
Output Disable to Output Float 0 50 0 60 ns
(Note 3)
t
OH
Output Hold from Addresses,
(Note 3) CE or OE , Whichever 0 0
Occurred First
Capacitance (Note 3) T
A
= +25˚C, f = 1 MHz
Symbol Parameter Conditions Typ Max Units
C
IN
Input Capacitance VIN = 0V 12 20 pF
C
OUT
Output Capacitance V
OUT
= 0V 13 20 pF
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 9)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Note 7) (Note 8) (Note 10)
Note 2: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 3: This parameter is only sampled and is not 100% tested.
Note 4: OE may be delayed up to t
ACC
- tOE after the falling edge of CE without impacting t
ACC
.
Note 5: The tDF and tCF compare level is determined as follows:
High to TRI-STATE™, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 6: TRI-STATE may be attained using OE or CE.
Note 7: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 8: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 9: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 10:VPP may be connected to VCC except during programming.
Note 11:Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol Parameter Conditions Min Typ Max Units
t
AS
Address Setup Time 1 µs
t
OES
OE Setup Time 1 µs
t
CES
CE Setup Time OE = V
IH
1 µs
t
DS
Data Setup Time 1 µs
t
VPS
VPP Setup Time 1 µs
t
VCS
VCC Setup Time 1 µs
t
AH
Address Hold Time 0 µs
t
DH
Data Hold Time 1 µs
t
DF
Output Enable to Output Float Delay CE = V
IL
060ns
Address Valid
Valid Output
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2.0V
0.8V
(Note 3)
(Note 3)
t
DF
(Note 4, 5)
(Note 4, 5)
t
DH
Hi-Z
t
OE
ACC
t
CF
t
Hi-Z
DS011376-4
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15) (Continued)
Symbol Parameter Conditions Min Typ Max Units
t
PW
Program Pulse Width 45 50 105 µs
t
OE
Data Valid from OE CE = V
IL
100 ns
I
PP
VPP Supply Current during CE = V
IL
40 mA
Programming Pulse PGM = V
IL
I
CC
VCC Supply Current 50 mA
T
A
Temperature Ambient 20 25 30 °C
V
CC
Power Supply Voltage 6.25 6.5 6.75 V
V
PP
Programming Supply Voltage 12.5 12.75 13.0 V
t
FR
Input Rise, Fall Time 5 ns
V
IL
Input Low Voltage 0.0 0.45 V
V
IH
Input High Voltage 2.4 4.0 V
t
IN
Input Timing Reference Voltage 0.8 2.0 V
t
OUT
Output Timing Reference Voltage 0.8 2.0 V
Programming Waveforms (Note 14)
Note 12:Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 13:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 14:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 15:During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.
t
AS
Program
Program Verify
Address N
t
DF
Hi-Z
t
DS
t
DH
t
VCS
t
VPS
t
PW
t
OES
t
OE
2.0V
0.8V
2.0V
0.8V
6.25V
12.75V
2.0V
0.8V
2.0V
0.8V
Addresses
Data
OE
CE
V
CC
V
PP
0.8V
PGM
t
CES
Data Out Valid
ADD N
Data In Stable
ADD N
DS011376-5
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Turbo LV Programming Algorithm Flow Chart
FIGURE 1.
VCC = 6.5V VPP = 12.75V
n = 0
ADDRESS = FIRST LOCATION
CHECK ALL BYTES
1ST: V
CC
= VPP = 5.0V
2ND: V
CC
= VPP = 3.0V
PROGRAM ONE 50µs PULSE
INCREMENT n
ADDRESS = FIRST LOCATION
VERIFY
BYTE
n = 10?
DEVICE
FAILED
LAST
ADDRESS
?
INCREMENT
ADDRESS
n = 0
PROGRAM ONE
50 µs
PULSE
INCREMENT
ADDRESS
VERIFY
BYTE
LAST
ADDRESS
?
PASS
NO
FAIL
YES
YES
PASS
NO
FAIL
NO
YES
DS011376-6
Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in . It should
be noted that all inputs for the six modes are at TTL levels. The
power supplies required are VCC and VPP. The VPP power supply
must be at 12.75V during the three programming modes, and must
be at 3.3V in the other three modes. The VCC power supply must
be at 6.5V during the three programming modes, and at 3.3V in the
other three modes.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to
gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address access time
(t
ACC
) is equal to the delay from CE to output (tCE). Data is available
at the outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least t
ACC
–
tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 66 mW to 66 µW. The EPROM is
placed in the standby mode by applying a CMOS high signal to the
CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control
function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 16 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 µs pulse. (The standard
National Semiconductor Algorithm may also be used but it will
have longer programming time.)
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description (Continued)
MODE SELECTION
The modes of operation of the NM27LV210 are listed in Table 1. A single power supply is required in the read mode. All inputs are TTL
levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins CE OE PGM V
PP
V
CC
Outputs
Mode
Read V
IL
V
IL
X X 3.3V D
OUT
(Note 16)
Output Disable X V
IH
X X 3.3V High Z
Standby V
IH
X X X 3.3V High Z
Programming V
IL
V
IH
V
IL
12.75V 6.25V D
IN
Program Verify V
IL
V
IL
V
IH
12.75V 6.25V D
OUT
Program Inhibit V
IH
X X 12.75V 6.25V High Z
Note 16:X can be VIL or VIH.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
VIL and VPP at 12.75V will program that EPROM. A TTL high level
CE input inhibits the other EPROM’s from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 6.25V. VPP must be at VCC, except during
programming and program verify.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the
NM27LV210 is “8FD6”, where “8F” designates that it is made by
Fairchild Semiconductor, and “D6” designates a 1 Megabit (64K
x 16) part.
The code is accessed by applying 12V ±0.5V to address pin A9 .
Addresses A1 –A8 ,A10 –A15 , and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
at VIH for the device code. The code is read on the lower eight data
pins, O0 –07 . Proper code access is only guaranteed at 25°C ±
5°C.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated V
CC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
TABLE 2. Manufacturer’s Identification Code
Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(21) (31) (12) (13) (14) (15) (16) (17) (18) (19) Data
Manufacturer Code V
IL
12V1 00 011 118F
Device Code V
IH
12V1 10 101 10D6
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
44-Lead Plastic Chip Carrier (V)
Order Number NM27LV210XXX
Package Number V44A
6 1 44 40
39
29
17
17
18 28
0.050
[1.27]
TYP
0.500
[12.70]
TYP
0.650
+0.006
–0.000
16.51
+0.15
0
PIN 1 IDENT
0.690 ± 0.005
[17.53 –0.13]
TYP
0.045
[1.14]
45°X
0.026–0.032
[0.66–0.81]
0.017 ±0.021
[0.43 ±0.10]
0.045
[1.14]
0.020
[0.51]
0.610 ±0.020
[15.49 ±0.51]
0.105 ±0.015
[2.67 ±0.38]
TYP
TYP
MIN TYP
Seating
plane
TYP
0.165–0.180
[4.19–4.57]
TYP
TYP
45°X
0.004 [0.10]
Physical Dimensions inches (millimeters) unless otherwise noted
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor
Americas Europe Hong Kong Japan Ltd.
Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku
English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan
Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840
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