Datasheet NM27LV010TE150, NM27LV010T250, NM27LV010T200, NM27LV010Q250, NM27LV010BT300 Datasheet (Fairchild Semiconductor)

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

General Description

The NM27LV010 is a high performance Low Voltage Electrically Programmable Read Only Memory. It is manufactured using Fairchild’s AMG™ EPROM technology. This technology allows the part to operate at speeds as fast as 200 ns.

This Low Voltage and Low Power EPROM is designed with power sensitive hand held and portable battery products in mind. This allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and HDD.

Small outline packages are just as critical to portable applications as Low Voltage and Low Power.

The NM27LV010 is one member of Fairchild’s growing Low Voltage product Family.

Block Diagram

July 1998

Features

■ 3.0V to 3.6V operation

■ 200 ns access time

■ Low current operation

—8 mA ICC active current @ 5 MHz (typ.) —20µA ICC standby current @ 5 MHz (typ.)

■ Ultra low power operation —66 µW standby power @ 3.3V —50 mW active power @ 3.3V

■ Surface mount package options| —32-pin TSOP —32-pin PLCC

DS011377-1

AMG™ is a trademark of WSI, Incorporated.

GND V

Output Enable,

Chip Enable &

Program Logic

Decoder

Output Buffers

1,048,576-Bit

Cell Matrix

0 - A16

Address

Inputs

Data Outputs O

0 - O7

PGM

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Connection Diagrams

PLCC Pin Configuration

Top View

TSOP Pin Configuration

Top View

Commercial Temperature Range (0°C to +70°C) VCC = 3.3 ± 0.3

Parameter/Order Number Access Time (ns)

NM27LV010 V, T 200 200 NM27LV010 V, T 250 250

Pin Names

A0–A16 Addresses

CE Chip Enable OE Output Enable

O0–O7 Outputs

PGM Program

XX Don’t Care (During Read)

Programming Voltage

Industrial Temperature Range (-40°C to +85°C) VCC = 3.3 ± 0.3

Parameter/Order Number Access Time (ns)

NM27LV010 VE, TE 200 NM27LV010 VE, TE 250

Package Types: NM27LV010 V, T V = PLCC T = TSOP

• All packages conform to the JEDEC standard.

• All versions are guaranteed to function for slower speeds.

• Consult the Fairchild Sales office on new released products and packages.

• Consult the Fairchild representative for custom products for your specific application.

OE A

CE O

A12A15A16XX/VPPVCCXX/PGM

O1O

GND

O3O4O5O

5 6 7 8 9 10 11 12 13

29 28 27 26 25 24 23 22 21

14 15 16 17 18 19 20

4 3 2 1 32 31 30

PGM

OE A

CE O7

O4 O

O1 O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

8 x 20 MM

TSOP

DS011377-2

DS011377-6

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Absolute Maximum Ratings (Note 1)

Storage Temperature -65°C to +150°C All Input Voltages except A9 with

Respect to Ground (Note 10) -0.6V to +7V VPP and A9 with Respect to Ground -0.6V to +14V VCC Supply Voltage with

Respect to Ground -0.6V to +7V ESD Protection >2000V

All Output Voltages with VCC + 1.0V

Respect to Ground (Note 10) to GND - 0.6V

Operating Range

Range Temperature V

Tolerance

Commercial 0°C to +70°C 3.3V ±0.3V Industrial -40°C to +85°C 3.3V ±0.3V

DC Electrical Characteristics Over Operating Range with V

= V

Symbol Parameter Test Conditions Min Max Units

Input Low Level -0.3 0.7 V

Input High Level 2.0 VCC + 0.3 V

OL1

Output Low Voltage (TTL) IOL = 2.0 mA 0.4 V

OH1

Output High Voltage (TTL) IOH = -2.0 mA 2.4 V

OL2

Output Low Voltage IOL = 100 µA 0.2 V

OH2

Output High Voltage (CMOS) IOH = -100 µAV

- 0.3

SB1

VCC Standby Current CE = VCC ± 0.3V 50 µA (CMOS)

SB2

VCC Standby Current (TTL) CE = V

100 µA

VCC Active Current CE = OE = VIL, f = 5 MHz 15 mA

I/O = 0 µA

VPP Supply Current VPP = V

10 µA

VPP Read Voltage VCC - 0.7 V

Input Load Current VIN = 3.0V or GND 1 µA

Output Leakage Current V

OUT

= 3.0V or GND -1 10 µA

AC Electrical Characteristics Over Operating Range with V

= V

Symbol Parameter 200 250 Units

Min Max Min Max

ACC

Address to Output Delay 200 250 ns

CE to Output Delay 200 250

OE to Output Delay 70 75

Output Disable to Output Float 50 50

(Note 2)

Output Hold from Addresses,

(Note 2) CE or OE , Whichever 0 0

Occurred First

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Capacitance (Note 2) T

= +25°C, 1 = 1 MHz

Symbol Parameter Conditions Typ Max Units

Input Capacitance VIN = 0V 9 15 pF

OUT

Output Capacitance V

OUT

= 0V 12 15 pF

AC Test Conditions

Output Load 1 TTL Gate and CL = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level

Inputs 0.8V and 2V

Outputs 0.8V and 2V

AC Waveforms (Note 6) , (Note 7) , and (Note 9)

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t

ACC

- tCE after the falling edge of CE without impacting t

ACC

Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured V

OH1

(DC) - 0.10V;

Low to TRI-STATE, the measured V

OL1

(DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2 µF ceramic capacitor be used on every device

between VCC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.

CL: 100pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming. Note 10:Inputs and outputs can undershoot to -2.0V for 20 ns Max.

Address Valid

Valid Output

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

ADDRESS

OUTPUT

2.0V

0.8V

(Note 3)

(Note 2, 4, 5)

Hi-Z

ACC

DS011377-3

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Programming Characteristics (Note 11), (Note 12), (Note 13) and (Note 14)

Symbol Parameter Conditions Min Typ Max Units

Address Setup Time 1 µs

OES

OE Setup Time 1 µs

CES

CE Setup Time 1 µs

Data Setup Time 1 µs

VPS

VPP Setup Time 1 µs

VCS

VCC Setup Time 1 µs

Address Hold Time 0 µs

Data Hold Time 1 µs

Output Enable to Output CE/PGM = V

060ns

Float Delay

Program Pulse Width 45 50 105 µs

Data Valid from OE CE/PGM = V

100 ns

VPP Supply Current CE/PGM = V

20 mA

during Programming Pulse

VCC Supply Current 20 mA

Temperature Ambient 20 25 30 °C

Power Supply Voltage 6.25 6.5 6.75 V

Programming Supply Voltage 12.5 12.75 13.0 V

Input Rise, Fall Time 5 ns

Input Low Voltage 0.0 0.45 V

Input High Voltage 2.4 4.0 V

Input Timing Reference Voltage 0.8 2.0 V

OUT

Output Timing Reference Voltage 0.8 2.0 V

Programming Waveform (Note 13)

Note 11:Fairchild’s standard product warranty applies to devices programmed to specifications described herein. Note 12:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removedfrom a board with

voltage applied to VPP or VCC. Note 13:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device.

Note 14:During power up the PGM pin must be brought high (≥ VIH) either coincident with or before power is applied to VPP.

Program

Program Verify

Address N

Hi-Z

VPS

2.0V

0.8V

2.0V

0.8V

Addresses

Data

CES

Data Out Valid

ADD N

Data In Stable

ADD N

12.75V

6.25V

VCS

PGM

OES

2.0V

0.8V

2.0V

0.8V

DS011377-4

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

LV Turbo Programming Algorithm Flow Chart

FIGURE 1.

VCC = 6.5V VPP = 12.75V

n = 0

ADDRESS = FIRST LOCATION

CHECK ALL BYTES

1ST: V

= VPP = 5.0V

2ND: V

= VPP = 3.0V

PROGRAM ONE 50µs PULSE

INCREMENT n

ADDRESS = FIRST LOCATION

VERIFY

BYTE

n = 10?

DEVICE

FAILED

LAST

ADDRESS

INCREMENT

ADDRESS

n = 0

PROGRAM ONE

50 µs

PULSE

INCREMENT

ADDRESS

VERIFY

BYTE

LAST

ADDRESS

PASS

FAIL

YES

PASS

FAIL

YES

DS011377-5

Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 3.3V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 3.3V in the other three modes.

Read Mode

The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (t

ACC

) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least t

ACC

–tOE.

Standby Mode

The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 50 mW to 0.17 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).

Output OR-Tying

Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the

“1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure.

The EPROM is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a

0.1 µF capacitor be placed across VPP and VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the LV Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used, but it will have longer programming time.)

The EPROM must not be programmed with a DC signal applied to the PGM input.

Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM.

Program Inhibit

Programming multiple EPROM’s in parallel with different data is also easily accomplished. Except for CE, all like inputs (including OE and PGM) of the parallel EPROM may be common. A TTL low level program pulse applied to an EPROM’s PGM input with CE at VIL and VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROM’s from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 6.25V. VPP must be at VCC, except during programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the NM27LV010 is “8F86”, where “8F” designates that it is made by Fairchild Semiconductor, and “86” designates a 1 Megabit (128k x 8) part.

The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A16, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the lower eight data pins, O0–07. Proper code access is only guaranteed at 25°C ± 5°C.

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Functional Description (Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å – 4000Å range.

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 30W-sec/cm2.

The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. When a lamp has aged, the system should be checked to make certain full erasure is occur-

ring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated V

transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.

Mode Selection

The modes of operation of the NM27LV010 are listed in Table 1. A single 3.3V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.

TABLE 1. Modes Selection

Pins CE OE PGM V

Outputs

Mode

Read V

XVCC3.3V D

OUT

Output Disable X (Note 15) V

XVCC3.3V High Z

Standby V

XXVCC3.3V High Z

Programming V

12.75V 6.25V D

Program Verify V

12.75V 12.75V D

OUT

Program Inhibit V

X 12.75V 6.25V High Z

Note 15: X can be VIL or VIH .

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex

(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data

Manufacturer Code

12V100011118F

Device Code V

12V1000011086

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

32-Lead TSOP Package (T)

Order Number NM27LV010TXXX

Package Number MBH32A

Physical Dimensions inches (millimeters) unless otherwise noted

18.4 ± 0.1

20.0 ± 0.2

8.0 ± 0.2

0.150±0.08 (Leadframe Thickness)

0.5

0°-5°

0.15-0.25 TYP

0.10

See Detail A

1.27 MAX

0-0.25

0.4-0.6

DETAIL A

Typical

0.96 - 1.06

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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM

Physical Dimensions inches (millimeters) unless otherwise noted

32-Lead PLCC Package

Order Number NM27LV010VXXX

Package Number VA32A

0.007[0.18]

F-G

0.007[0.18]

D-E

0.449-0.453

[11.40-11.51]

0.045

[1.143]

0.000-0.010 [0.00-0.25]

Polished Optional

0.585-0.595

[14.86-15.11]

0.549-0.553

[13.94-14.05]

-B-

-F-

-E-

-G-

0.050

2014

-D-

0.007[0.18]

D-E

0.002[0.05]

-A-

0.485-0.495

[12.32-12.57]

0.007[0.18]

F-G

0.002[0.05]

0.007[0.18]

D-E, F-G

0.015[0.38]

C D-E, F-G

0.490-0530

[12.45-13.46]

0.078-0.095 [1.98-2.41]

0.013-0.021 [0.33-0.53]

0.004[0.10]

0.123-0.140 [3.12-3.56]

See detail A

-J-

-C-

0.400

[10.16]

( )

TYP

0.541-0.545

[13.74-13-84]

0.023-0.029 [0.58-0.74]

0.106-0.112 [2.69-2.84]

60°

0.015 [0.38]

Base Plane

-H-

Min Typ

0.007[0.18]

D-E, F-G

0.010[0.25]

B A

D-E, F-G

0.118-0.129 [3.00-3.28]

45°X

0.042-0.048 [1.07-1.22]

0.026-0.032 [0.66-0.81]

Typ

0.0100 [0.254]

0.030-0.040 [0.76-1.02]

0.005 [0.13]

Max

0.020 [0.51]

0.045 [1.14]

Detail A

Typical

Rotated 90°

0.027-0.033 [0.69-0.84]

0.025 [0.64]

Min

0.025 [0.64]

Min

0.031-0.037 [0.79-0.94]

0.053-0.059 [1.65-1.80]

0.006-0.012 [0.15-0.30]

0.019-0.025 [0.48-0.64]

0.065-0.071 [1.65-1.80]

0.021-0.027 [0.53-0.69]

Section B-B

Typical

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku

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