Datasheet NM27C240NE120, NM27C240VE150, NM27C240VE120, NM27C240V150, NM27C240QE150 Datasheet (Fairchild Semiconductor)
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
NM27C240
4,194,304-Bit (256k x 16) High Performance
CMOS EPROM
General Description
The NM27C240 is a high performance Electrically Programmable
UV erasable ROM (EPROM). It contains 4,194,304 bits configured as 256k x 16 bits. It is offered in both erasable versions for
prototyping and early production applications as well as nonerasable, plastic packaged versions that are ideal for high volume
and automated assembly applications.
The NM27C240 operates from a single 5V ±10% supply in the
read mode.
The NM27C240 is offered in both DIP and surface mount packages. The DIP package is a 40-pin dual-in-line ceramic with a
quartz window to allow erasing. The surface mount package is a
44-pin PLCC that is offered in OTP.
This EPROM is manufactured using Fairchild’s proprietary AMG™
EPROM technology for an excellent combination of speed and
economy while providing excellent reliability.
Block Diagram
July 1998
Features
■ High performance CMOS
—100 ns access time
■ Fast turn-off for microprocessor compatibility
■ Simplified upgrade path
—VPP and PGM are “Don’t Care” during normal read
operation
■ Compatible with 27240 and 27C240 EPROMs
■ JEDEC standard pin configuration
—40-pin DIP package
—44-pin PLCC package
■ Manufacturer’s identification code
■ Fast programming algorithm
AMG™ is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
V
cc
GND
V
pp
OE
CE/PGM
Output Enable
Chip Enable, and
Program Logic
Y
Decoder
X
Decoder
Output
Buffers
4,194,304-Bit
Cell Matrix
A
0 - A17
Address
Inputs
Data Outputs O
0 - O15
DS011949-1
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C240 pins.
Commercial Temperature Range
(0°C to +70°C) VCC = 5V ±10%
Parameter/Order Number Access Time (ns)
NM27C240 Q, V, N 100 100
NM27C240 Q, V, N 120 120
NM27C240 Q, V, N 150 150
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
Package types: NM27C240 Q, V, N XXX
Q = Quartz-Windowed Ceramic DIP Package
V = PLCC Package
N = Plastic DIP Package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.
Pin Names
A0–A15 Addresses
CE/PGM Chip Enable/Program
OE Output Enable
O0–O15 Outputs
XX Don’t Care (During Read)
NC No Connect
Extended Temperature Range
(-40° to +85°C) VCC = 5V ±10%
Parameter/Order Number Access Time (ns)
NM27C240 QE, VE, NE 120 120
NM27C240 QE, VE, NE 150 150
PLCC Pin Configuration
27C210 27C220 27C280
A
18
CE/PGM
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
GND
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
OE/V
PP
XXV
PP
CE
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
GND
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
OE
XXV
PP
CE
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
GND
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
OE
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
V
CC
XX/PGM
NC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
V
CC
PGM
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
XX/V
PP
CE/PGM
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
GND
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
OE
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
27C280 27C220 27C210
O
12
O
11
O
10
O
9
O
8
GND
NC
O
7
O
6
O
5
O
4
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
O13O14O15CE/PGM
XX/VPPNC
A17A16A15A
14
O3O2O1O
0
OE
NC
A0A1A2A3A
4
1
23456
7
8
9
10
11
12
13
14
15
16
17
4041424344
38
37
36
35
34
33
32
31
30
2221201918 282726252423
29
39
V
CC
DIP
NM27C240
DS011949-3
DS011949-2
Top View
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Storage Temperature -65°C to +150°C
All Input Voltages except A9 with
Respect to Ground (Note 10) -0.6V to +7V
VPP and A9 with
Respect to Ground -0.6V to +14V
VCC Supply Voltage with
Respect to Ground -0.6V to +7V
ESD Protection >2000V
All Output Voltages with Respect
to Ground (Note 10) VCC + 1.0V to GND - 0.6V
Operating Range
Range Temperature V
CC
Tolerance
Commercial 0°C to +70°C +5V ±10%
Industrial -40V°C to +85°C +5V ±10%
DC Read Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter Conditions Min Max Units
V
IL
Input Low Level -0.5 0.8 V
V
IH
Input High Level 2.0 VCC +1 V
V
OL
Output Low Voltage IOL = 2.1 mA 0.4 V
V
OH
Output High Voltage IOH = -2.5 mA 3.5 V
I
SB1
VCC Standby Current (CMOS) CE = VCC ±0.3V 100 µA
I
SB2
VCC Standby Current (TTL) CE = V
IH
1mA
ICCVCC Active Current CE = OE = VIL, I/O = 0 mA f=5 MHz 40 mA
I
PP
VPP Supply Current VPP = V
CC
10 µA
I
LI
Input Load Current VIN = 5.5V or GND -1 1 µA
I
LO
Output Leakage Current V
OUT
= 5.5V or GND -10 10 µA
AC Read Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter 100 120 150 Units
Min Max Min Max Min Max
t
ACC
Address to Output Delay 100 120 150 ns
t
CE
CE to Output Delay 100 120 150
t
OE
OE to Output Delay 50 50 50
tDF (Note 2) Output Disable to Output Float 35 35 45
tOH (Note 2) Output Hold from Addresses CE or 0 0 0
OE , Whichever Occurred First
Capacitance T
A
= +25˚C, f = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
C
IN
Input Capacitance VIN = 0V 12 20 pF
C
OUT
Output Capacitance V
OUT
= 0V 13 20 pF
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Notes 6, 7) (Note 9)
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
–tOE after the falling edge of CE without impacting t
ACC
.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10:Inputs and outputs can undershoot to -2.0V for 20 ns Max.
t
OH
t
DF
Notes 4, 5
t
CF
Notes 4, 5
t
ACC
Note 3
t
OE
Note 3
High Z2.0V
0.8V
Output
2.0V
0.8V
OE
2.0V
0.8V
CE
2.0V
0.8V
Adresses
High Z
Addresses Valid
t
CE
DS011949-4
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
DC Electrical Characteristics (Notes 11, 12, 13, 14)
Symbol Parameter Conditions Min Typ Max Units
t
AS
Address Setup Time 1 µs
t
OES
OE Setup Time 1 µs
t
DS
Data Setup Time 1 2.4 µs
t
VPS
VPP Setup Time 1 µs
t
VCS
VCC Setup Time 1 µs
t
AH
Address Hold Time 0 µs
t
DH
Data Hold Time 1 µs
t
DF
Output Enable to Output Float Delay CE = V
IL
060ns
t
PW
Program Pulse Width 45 50 105 µs
t
OE
Data Valid from OE CE = V
IL
100 ns
I
PP
VPP Supply Current during Programming Pulse CE = VIL, PGM = V
IL
30 mA
I
CC
VCC Supply Current 30 mA
T
A
Temperature Ambient 20 25 30 °C
V
CC
Power Supply Voltage 6.25 6.5 6.75 V
V
PP
Programming Supply Voltage 12.5 12.75 13.0 V
t
FR
Input Rise, Fall Time 5 ns
V
IL
Input Low Voltage 0.0 0.45 V
V
IH
Input High Voltage 2.4 4.0 V
t
IN
Input Timing Reference Voltage 0.8 2.0 V
t
OUT
Output Timing Reference Voltage 0.8 2.0 V
Programming Waveforms (Note 13)
Note 11:Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14:During power up the CE/PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.
t
PW
2.0V
0.8V
12.75V
6.25V
2.0V
0.8V
Adresses
Address N
t
DF
Program Program Verify
Data In Stable
Add N
Data Out Valid
Add N
Data
V
CC
V
PP
t
AS
t
AH
t
OEStOE
High Z
2.0V
0.8V
OE
CE/PGM
t
DS
2.0V
0.8V
t
DH
t
VCS
t
VPS
DS011949-5
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
FIGURE 1.
VCC = 6.5V VPP = 12.75V
n = 0
ADDRESS = FIRST LOCATION
CHECK ALL BYTES
1ST: V
CC
= VPP = 6.0V
2ND: V
CC
= VPP = 4.2V
PROGRAM ONE 50µs PULSE
INCREMENT n
ADDRESS = FIRST LOCATION
VERIFY
BYTE
n = 10?
DEVICE
FAILED
LAST
ADDRESS
?
INCREMENT
ADDRESS
n = 0
PROGRAM ONE
50 µs
PULSE
INCREMENT
ADDRESS
VERIFY
BYTE
LAST
ADDRESS
?
PASS
NO
FAIL
YES
YES
PASS
NO
FAIL
NO
YES
DS011949-6
Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and VPP. VCC power supply
must be at 12.75V during the three programming modes, and must
be at 5V in the other three modes. The VCC power supply must be
at 6.5V during the three programming modes, and at 5V in the
other three modes.
Mode Selection
The modes of operation of the NM27C240 are listed in Table 1. A
single 5V power supply is required in the read mode. All inputs are
TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
Mode CE/ OE V
PP
VCCOutputs
PGM
Read V
IL
V
IL
X 5.0V D
OUT
Output Disable X V
IH
X 5.0V High Z
Standby V
IH
X X 5.0V High Z
Programming V
IL
V
IH
12.75V 6.25V D
IN
Program V
IL
V
IL
12.75V 6.25V D
OUT
Verify
Program V
IH
X 12.75V 6.25V High Z
Inhibit
Note 15: X can be VIL or VIH.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for selection. Output
Enable (OE) is the output control and should be used to gate data
to the output pins, independent of the device selection. Assuming
that the addresses are stable, address access time (t
ACC
) is equal
to the delay from CE to output (tCE). Data is available at the outputs
tOE after falling edge of OE, assuming that CE has been low and
addresses have been stable for at least t
ACC
- tOE.
Standby Mode
The EPROM standby mode reduces the active power dissipation
by over 99%, from 165 mW to 0.55 mW. The EPROM is placed in
the standby mode by applying a CMOS high signal to the CE input.
When in standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple connections. The 2-line control function
allows for:
1. the lowest possible memory power dissipation, and
2. the complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
Initially, and after erasure, all bits of the EPROM are in the “1’s”
state. Data is introduced by selectively programming “0’s” into the
desired bit locations. Although only “0’s” will be programmed, both
“1’s” and “0’s” can be presented in the data word. The only way to
change a “0” to a “1” is by ultraviolet light erasure.
The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 16 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
When the address and data are stable, and active low, TTL
program pulse is applied to the PGM input. A program pulse must
be applied at each address location to be programmed. The
EPROM is programmed with the Turbo Programming Algorithm
shown in Figure 1. Each Address is programmed with a series of
50 µs pulses until it verifies good, up to a maximum of 10 pulses.
Most memory cells will program with a single 50 µs pulse. (The
standard National Semiconductor algorithm may also be used but
it will have longer programming time.)
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
VIL and VPP at 12.75V will program that EPROM. A TTL high level
CE input inhibits the other EPROM’s from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 12.75V. VPP must be at VCC, except during
programming and program verify.
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Functional Description (Continued)
After Programming
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of photo
currents.
Manufacturer’s Identification Code
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The manufacturer’s identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the
NM27C240 is “8FEE”, where “8F” designates that it is made by
Fairchild Semiconductor, and “EE” designates a 4 Megabit (256k
x 16) part.
The code is accessed by applying 12V ±0.5% to address pin A9.
Addresses A1–A8, A10–A15, and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
at VIH for the device code. The code is read on the lower eight data
pins, O0–O7. Proper code access is only guaranteed at 25°C
±5°C.
Erasure Characteristics
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000Å–4000Å range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of
2537Å. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
Lamps lose intensity as they age. When a lamp is changed, the
distance has changed, or the lamp has aged, the system should
be checked to make sure full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
System Consideration
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated V
CC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
TABLE 2. Manufacturer’s Identification Code
Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(21) (31) (12) (13) (14) (15) (16) (17) (18) (19) Data
Manufacturer Code V
IL
12V1 00011 11 8F
Device Code V
IH
12V1 11011 10 EE
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
40-Lead Ceramic Dual-In-Line Package (Q)
Order Number NM27C240Qxxx
Package Number J40BQ
44-Lead Plastic Chip Carrier (V)
Order Number NM27C240Vxxx
Package Number V44A
Physical Dimensions inches (millimeters) unless otherwise noted
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
UV Window size and configuration
determined by device size
0.90 – 0.110
[2.29 – 2.79]
TYP
86° 94° TYP
0.098
[2.49]
MAX
(Both Ends)
0.180
[4.57]
MAX
0.040
[1.02]
TYP
0.005
[0.13]
MIN
Glass
Sealant
0.030 - 0.055
(0.76 -1.40)
RAD TYP
0.020±0.070
[0.51 –1.78]
0.125 – 0.200
[3.18 – 5.08]
0.150
[3.81]
MIN
0.015 - 0.035
(0.38 - 0.89)
RAD
2.096
(53.24)
MAX
0.180
[4.57]
MAX
0.225
[5.72]
MAX
0.610
(15.49)
Max
Glass
0.590
(14.99)
Max
Ceramic
0.010
[0.25]
MAX
0.590±0.620
[14.99 – 15.75]
0.008 – 0.012
[0.20 – 0.30]
0.625 – 0.710
[15.88 – 18.03]
90°- 100°
0.590-0630
[14.99-16.00]
0.013-0.021
[0.33-0.53]
0.165-0.180
[4.19-4.57]
0.020
[0.51]
MIN TYP
TYP
TYP
0.026-0.032
[0.66-0.81]
TYP
0.045
[1.14]
45° X
0.045
[1.14]
45°X
PIN 1 INDENT
29
39
4044
1
5
28
18
17
7
0.650-0.656
[16.51-16.66]
0.50
[1.27]
Typ
0.500
[12.70]
Typ
TYP
0.685-0.695
[17.40–17.65]
TYP
0.090-0.130
[2.29-3.30]
TYP
Page 10
10
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
40-Lead Plastic Molded Dual-In-Line (N)
Order Number NM27C240Nxxx
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0.0.18 ± 0.003
(0.457 ± 0.076)
86° 94°
TYP
0.125–0.150
(3.048–3.81)
0.100 ± 0.010
(2.540 ± 0.254)
0.040 - 0.090
(1.016 - 2.286)
0.062
(1.575)
RAD
1.90 – 2.10
(48.26 – 53.34)
0.125–0.165
(3.175–4.191)
0.490 - 0.550
(12.446 - 13.97)
0.580
(14.73)
MIN
0.008±0.015
(0.203±0.381)
95°±5°
PIN #1 IDENT
0.145–0.210
(3.683–5.334)
0.015
(0.381)
MIN
0.050
(1.270)
0.035 - 0.070
(0.889 - 1.778)
0.600–0.620
(15.240–15.748)
0.030
(0.762)
MAX
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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