Datasheet NM27C020V150, NM27C020T120, NM27C020Q150, NM27C020VE150, NM27C020VE120 Datasheet (Fairchild Semiconductor)

...

Page 1

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

General Description

The NM27C020 is a high speed 2 Megabit CMOS UV-EPROM manufactured on Fairchild’s advanced sub-micron technology. Utilizing the AMG architecture, this advanced CMOS process delivers high speeds while consuming low power.

The NM27C020 provides microprocessor-based systems extensive storage capacity for large portions of operating systems and application software. Its 100ns access time provides no-wait-state operation with high-performance CPUs.

The NM27C020 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequentlyused software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The NM27C020 is manufactured using Fairchild’s advanced CMOS AMG EPROM technology, and is one member of a high density Fairchild EPROM series family which range in densities up to 4Mb.

Block Diagram

July 1998

Features

■ High performance CMOS — 100 ns access time

■ Simplified upgrade path —VPP and PGM are “Don’t Care” during normal read operation

■ Manufacturers identification code

■ JEDEC Standard Pin Configuration

— 32-pin CERDIP package — 32-pin PLCC package — 32-pin PDIP package

Output Enable,

Chip Enable, and

Program Logic

Y Decoder

X Decoder

. . . . . . . . .

Output Buffers

2,097,152-Bit

Cell Matrix

Data Outputs O0 - O

GND

PP OE

PGM

A0 - A

Address

Inputs

DS010835-1

Page 2

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Connection Diagrams

Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number Access Time (ns)

NM27C020 Q, V, N 100 100 NM27C020 Q, V, N 120 120 NM27C020 Q, V, N 150 150

All versions are guaranteed to function at slower speeds.

Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number Access Time (ns)

NM27C020 QE, VE, TE, NE 120 120 NM27C020 QE, VE, TE, NE 150 150

PLCC Pin Configuration

Top View

Pin Names

A0 –A17 Addresses CE Chip Enable OE Output Enable O0 –O7 Outputs PGM Program XX Don’t Care (During Read)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

XX/V

12 A

GND

27C512 27C256

GND

27C256 27C512

XX/PGM A

OE A

CE O

CE/PGM

OE/V

CE/PGM

XX/V

GND

27C040

XX/V

GND

27C010

A19 A

GND

27C080 27C040 27C080

CE O

OE/V

CE/PGM

27C010

XX/PGM

CE/PGM

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C020 pins.

A14 A13 A8 A9 A11 OE A10 CE O7

A7 A6 A5 A4 A3 A2 A1 A0

A12

A15

A16

VPP

VCC

PGM

A17

GND

O3O4O5

5 6 7 8 9 10 11 12 13

29 28 27 26 25 24 23 22 21

14 15 16 17 18 19 20

4 3 2 1 32 31 30

DS010835-10

DS010835-3

Page 3

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Access Time 100 = 100 ns 120 = 120 ns 150 = 150 ns

Operating Temp Blank = Commercial Temp. E = Extended Temp.

Packaging Q = Ceramic DIP V = PLCC N = PDIP

Memory Size 020 = 2 Mbit

Fairchild

Memory

EPROM

CMOS

Q 150ENM 27 C 020

Connection Diagrams (Continued)

Ordering Information

DS010835-9

Page 4

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Absolute Maximum Ratings (Note 1)

Storage Temperature -65°C to +125°C All Input Voltage Except A9 with

Respect to Ground (Note 13) -0.6V to +7V VPPand A9 with Respect to Ground -0.6V to +14V VCC Supply Voltage with

Respect to Ground -0.6V to +7V ESD Protection >2000V

All Output Voltages with

Respect to Ground (Note 13) VCC + 10V to GND -0.6V

Operating Range

Range Temperature VCCTolerance

Commercial 0°C to +70°C +5V ±10 Industrial -40°C to +85°C +5V ±10%

DC Read Characteristics Over Operating Range with V

= V

Symbol Parameter Test Conditions Min Max Units

Input Low Level -0.5 0.8 V

Input High Level 2.0 VCC +1 V

Output Low Voltage IOL = 2.1 mA -0.4 V

Output High Voltage IOH = -400 µA 3.5 V

SB1

(Note 4) VCC Standby Current (CMOS) CE = VCC ± 0.3V 100 µA

SB2

VCC Standby Current (TTL) CE = V

1mA

(Note 2) VCC Active Current CE, OE = V

Commercial 30 I/O = 0 mA, f = 5 MHz Industrial 30 mA Inputs = VIH or V

VPP Supply Current VPP = V

10 µA

VPP VPP Read Voltage VCC - 0.4 V

Input Load Current VIN = 5.5 or GND -1 1 µA

Output Leakage Current V

OUT

= 5.5V or GND -10 10 µA

AC Read Characteristics Over Operating Range with V

= V

Symbol Parameter 100 120 150 Units

Min Max Min Max Min Max

ACC

Address to Output Delay 100 120 150 ns

CE to Output Delay 100 120 150 ns

OE to Output Delay 40 45 50 ns

tDF (Note 3) Output Disable to Output Float 40 45 50 ns

Output Hold from Addresses, CE 0 0 0 ns or OE , Whichever Occurred First

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

Note 2: The supply current is the sum of ICC and IPP. The maximum current value is with Outputs O0 to O7 unloaded. Note 3: This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram. Note 4: CMOS inputs: VIL = GND 10.3V, VIH = VCC 10.3V.

Page 5

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

012345678

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

AC Read Characteristics (Continued)

ICC vs. Frequency

Frequency (MHz)

ICC vs. Temperature

Temperature (IC)

DS010835-7

DS010835-8

Page 6

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Capacitance T

= +25°C, f = 1 MHz (Note 5)

Symbol Parameter Conditions Typ Max Units

Input Capacitance VIN = 0V 9 15 pF

OUT

Output Capacitance V

OUT

= 0V 12 15 pF

AC Test Conditions

Output Load 1 TTL Gate and CL = 100 pF (Note 11) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level (Note 13)

Inputs 0.8V and 2V Outputs 0.8V and 2V

AC Waveforms (Notes 9, 10, 12)

Note 5: This parameter is only sampled and is not 100% tested. Note 6: OE may be delayed up to t

ACC

- tOE after the falling edge of CE without impacting t

ACC

Note 7: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured V

OH1

(DC) - 0.10V;

Low to TRI-STATE, the measured V

OL1

(DC) + 0.10V.

Note 8: TRI-STATE may be attained using OE or CE . Note 9: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 MF ceramic capacitor be used on every

device between VCC and GND.

Note 10:The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 11:1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.

CL: 100 pF includes fixture capacitance.

Note 12:VPP may be connected to VCC except during programming. Note 13:Inputs and outputs can undershoot to -2.0V for 20 ns Max.

Address Valid

Valid Output

Hi-Z

0.8V

ADDRESS

OUTPUT

0.8V

(Note 6)

(Note 7, 8)

Hi-Z

ACC

DS010835-4

Page 7

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Programming Characteristics (Notes 14, 15, 16, 17)

Symbol Parameter Condition Min Typ Max Units

Address Setup Time 1 µs

OES

OE Setup Time 1 µs

CES

CE Setup Time OE = V

1 µs

Data Setup Time 1 µs

VPS

VPP Setup Time 1 µs

VCS

VCC Setup Time 1 µs

Address Hold Time 0 µs

Data Hold Time 1 µs

Output Enable to Output CE = V

060ns

Float Delay

Program Pulse Width 45 50 105 µs

Data Valid from OE CE = V

100 ns

VPP Supply Current during CE = V

15 mA

Programming Pulse PGM = V

VCC Supply Current 20 mA

Temperature Ambient 20 25 30 °C

Power Supply Voltage 6.25 6.5 6.75 V

Programming Supply Voltage 12.5 12.75 13.0 V

Input Rise, Fall Time 5 ns

Input Low Voltage 0.0 0.45 V

Input High Voltage 2.4 4.0 V

Input Timing Reference Voltage 0.8 2.0 V

OUT

Output Timing Reference Voltage 0.8 2.0 V

Note 14:Fairchild’s standard product warranty applies only to devices programmed to specifications described herein. Note 15:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with

voltage applied to VPP or VCC. Note 16:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device.

Note 17: During power up the PGM pin must be brought high (≥V IH ) either coincident with or before power is applied to V PP .

Page 8

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Program

Verify

Address N

Data Out Valid

ADD N

Data In Stable

ADD N

Hi-Z

VCS

VPS

CES

OES

0.8V

6.25V

12.75V

0.8V

ADDRESS

DATA

PGM

Programming Waveforms (Note 16)

DS010835-5

Page 9

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Turbo Programming Algorithm Flow Chart

VCC = 6.5V VPP = 12.75V

n = 0

ADDRESS = FIRST LOCATION

CHECK ALL BYTES

1ST: V

= VPP = 6.0V

2ND: V

= VPP = 4.3V

PROGRAM ONE 50µs PULSE

INCREMENT n

ADDRESS = FIRST LOCATION

VERIFY

BYTE

n = 10?

DEVICE

FAILED

LAST

ADDRESS

INCREMENT

ADDRESS

n = 0

PROGRAM ONE

50 µs

PULSE

INCREMENT

ADDRESS

VERIFY

BYTE

LAST

ADDRESS

PASS

FAIL

YES

PASS

FAIL

YES

DS010835-6

FIGURE 1.

Note: The standard National Semiconductor Algorithm may also be used but it will have longer programming time.

Page 10

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Functional Description

DEVICE OPERATION

The six modes of operation of the device are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes.

Read Mode

The part has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, address access time (t

ACC

) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least t

ACC

–tOE.

Standby Mode

The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output OR-Tying

Because the part is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all selected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 14V on pin 1 (VPP) will damage the device. Initially, and after each erasure, all bits of the device are in the “1’s”

state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure.

The part is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 µF capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM.

MODE SELECTION

The modes of operation of the NM27C020 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.

TABLE 1. Modes Selection

Pins CE OE PGM V

Outputs

Mode

Read V

X X 5.0V D

OUT

(Note 18)

Output Disable X V

X X 5.0V H igh Z

Standby V

X X X 5.0V High Z

Programming V

12.75V 6.25V D

Program Verify V

12.75V 6.25V D

OUT

Program Inhibit V

X X 12.75V 6.25V High Z

Note 18:X can be VIL or VIH.

Page 11

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Functional Description (Continued)

Program Inhibit

Programming multiple EPROM’s in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE) of the parallel EPROM may be common. A TTL low level program pulse applied to an EPROM’s CE with VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROM’s from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify.

MANUFACTURER’S IDENTIFICATION CODE

The part has a manufacturer’s indentification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the NM27C020 is “8F8E,” where “8F” designates that it is made by Fairchild Semiconductor, and “8E” designates a 2 Megabit bytewide part.

The code is accessed by applying 12V ±0.5V to address pin A9. Addresses and control pins are held at VIL, except A0. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 –07 . Proper code access is only guaranteed at 25°C ± 5°C.

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths

in the 3000Å – 4000Å range. After programming, opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity X exposure time) for erasure should be a minimum of 15W-sec/cm2. The device should be placed within 1 inch of the lamp tubes during erasure. The device should be placed within 1 inch of the lamp tubes during erasure.

An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp. (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components and even system designs have been erroneously suspected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated V

transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex

(12) (26) (21) (19) (18) (17) (16) (15) (14) (13) Data

Manufacturer Code

12V100011118F

Device Code V

12V0000011107

Page 12

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number NM27C020Q

Package Number J32AQ

Physical Dimensions inches (millimeters) unless otherwise noted

1.660 MAX

R 0.025

R 0.030-0.055

TYP

UV WINDOW SIZE AND CONFIGURATION DETERMINED BY DEVICE SIZE

0.590-0.620

0.175 MAX

0.060-0.100 TYP

0.050-0.060 TYP

0.015-0.021 TYP

86°-94°

TYP

0.150 MIN TYP

0.015 -0.060 TYP

0.10

MAX

0.090-0.110 TYP

0.005 MIN TYP

0.225 MAX TYP

0.125 MIN TYP

90° - 100°

TYP

0.685

+0.025

-0.060

0.008-0.012 TYP

0.585 MAX

Page 13

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

32-Lead PDIP Package

Order Number NM27C020N

Physical Dimensions inches (millimeters) unless otherwise noted

1.64 – 1.66

(41.66 – 42.164)

0.062

(1.575)

RAD

Pin No. 1 IDENT

0.580

(14.73)

MIN

0.600 – 0.620

(15.240 – 15.748)

0.145 – 0.210

(3.683 – 5.334)

0.040 - 0.090

(1.016 – 2.286)

0.050

(1.270)

TYP

0.125 – 0.165

(3.175 – 4.191)

0.018 ±0.003

(0.457 ±0.078)

0.035 – 0.07

(0.889 – 1.778)

86°- 94°

TYP

0.120 – 0.150 (3.048 – 3.81)

0.015

(0.381)

0.100 ±0.010

(2.540 ±0.254)

90°–105°

0.008 - 0.015

(0.203 – 0.381)

0.490 – 0.550

(12.446 – 13.97)

Page 14

www.fairchildsemi.com

NM27C020 2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Physical Dimensions inches (millimeters) unless otherwise noted

32-Lead PLCC Package

Order Number NM27C020V

Package Number VA32A

0.007[0.18]

F-G

0.007[0.18]

D-E

0.449-0.453

[11.40-11.51]

0.045 [1.143]

0.000-0.010 [0.00-0.25]

Polished Optional

0.585-0.595

[14.86-15.11]

0.549-0.553

[13.94-14.05]

-B-

-F-

-E-

-G-

0.050

2014

-D-

0.007[0.18]

D-E

0.002[0.05]

-A-

0.485-0.495

[12.32-12.57]

0.007[0.18]

F-G

0.002[0.05]

0.007[0.18]

D-E, F-G

0.015[0.38]

C D-E, F-G

0.490-0530

[12.45-13.46]

0.078-0.095 [1.98-2.41]

0.013-0.021 [0.33-0.53]

0.004[0.10]

0.123-0.140 [3.12-3.56]

See detail A

-J-

-C-

0.400

[10.16]

( )

TYP

0.541-0.545

[13.74-13-84]

0.023-0.029 [0.58-0.74]

0.106-0.112 [2.69-2.84]

60°

0.015 [0.38]

Base Plane

-H-

Min Typ

0.027-0.033 [0.69-0.84]

0.025

[0.64]

Min

0.025 [0.64]

Min

0.031-0.037 [0.79-0.94]

0.053-0.059 [1.65-1.80]

0.006-0.012 [0.15-0.30]

0.019-0.025 [0.48-0.64]

0.065-0.071 [1.65-1.80]

0.021-0.027 [0.53-0.69]

Section B-B

Typical

0.007[0.18]

D-E, F-G

0.010[0.25]

B A

D-E, F-G

0.118-0.129 [3.00-3.28]

45°X

0.042-0.048 [1.07-1.22]

0.026-0.032 [0.66-0.81]

Typ

0.0100 [0.254]

0.030-0.040 [0.76-1.02]

0.005 [0.13]

Max

0.020 [0.51]

0.045 [1.14]

Detail A

Typical

Rotated 90°

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.

Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku

English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841