Datasheet NM25C041EM8, NM25C041LM8X, NM25C041M8X, NM25C041N, NM25C041M8 Datasheet (Fairchild Semiconductor)

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

March 1999

© 1999 Fairchild Semiconductor Corporation

NM25C041
4K-Bit Serial Interface CMOS EEPROM (Serial
Peripheral Interface (SPI™) Synchronous Bus)

General Description

The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral
Interface) CMOS EEPROM which is designed for high-reliability
non-volatile data storage applications. The SPI interface features
a byte-wide format (all data is transferred in 8-bit words) to
interface with the Motorola 68HC11 microprocessor, or equivalent,
at a 2.1MHz clock transfer rate. (This interface is considered the
fastest serial communication method.) This 4-wire SPI interface
allows the end user full EEPROM functionality while keeping pin
count and space requirements low for maximum PC board space
utilization.

The SPI interface requires four I/O pins on each EEPROM device:
Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data
Out (SO), as well as 2 other control pins: Write Protect (WP) and
HOLD (HOLD). The Write Protect pin can be used to disable the
Write operation and the HOLD pin is used to interrupt the SI
datastream and place the device in a Hold state during micropro­cessor instruction generation. Please refer to the following dia­grams and description for more details.

All programming cycles are completely self-timed and do not
require an ERASE, or similar setup, before programming any cells.
Programming can be performed in 3 modes, address (byte) write,
page (4 addresses/bytes) write or partial page write. Furthermore,
the EEPROM is provided with 4 levels of write protection wherein
the data, once programmed, cannot be altered. This is controlled

Block Diagram

by the Status Register and is described in greater detail within this
datasheet. In order to prevent spurious programming, the EEPROM
has both a Write Enable command, which is immediately disabled
after each programming operation, and a Write Protect (WP) pin,
which must be pulled HIGH to program.

Features

■ 2.1 MHz clock rate @ 2.7V to 5.5V

■ 4096 bits organized as 512 x 8

■ Multiple chips on the same 3 wire bus with separate chip

select lines

■ Self-timed programming cycle

■ Simultaneous programming of 1 to 4 bytes at a time

■ Status register can be polled during programming to monitor

RDY/BUSY

■ Both the Write Protect (WP) pin and 'auto-write disable after
programming' provides hardware and software write
protection

■ Block write protect feature to protect against accidental
writes

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP and 8-pin SO

DS800002-1

SPI™ is a trademark of Motorola Corporation.

Instruction

Decoder

Control Logic

and Clock

Generators

High Voltage

Generator

and

Program

Timer

Instruction

Register

Program
Enable

Data In/Out Register

8 Bits

Data Out

Buffer

Non-Volatile

Status Register

Decoder
1 of 512

Address
Counter/
Register

EEPROM Array

4096 Bits
(512 x 8)

Read/Write Amps

CS

HOLD

SCK

V

CC

V

SS

V

PP

WP

SI

SO

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N)

and SO Package (M8)

Top View

Pin Names

CS Chip Select Input

SO Serial Data Output
WP Write Protect
V

SS

Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Suspends Serial Data

V

CC

Power Supply

Ordering Information
NM 25 C XX LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SO

Temp. Range None 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 4.5V
LZ 2.7V to 4.5V and

<1µA Standby Current

Density/Mode 041 4K, mode 1

C CMOS

Interface 25 SPI

NM Fairchild Non-Volatile

Memory

CS

SO
WP
V

SS

V

CC

HOLD
SCK
SI

8
7
6
5

1
2
3
4

DS800002-2

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground
Lead Temperature (Soldering, 10 sec.) +300°C
ESD Rating 2000V

Operating Conditions

Ambient Operating Temperature

NM25C041 0°C to +70°C
NM25C041E -40°C to +85°C
NM25C041V -40°C to +125°C

Power Supply (VCC)

NM25C041 4.5V to 5.5V

DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V

Symbol Parameter Conditions Min Max Units

I

CC

Operating Current CS = V

IL

3mA

I

CCSB

Standby Current CS = V

CC

50 µA

I

IL

Input Leakage VIN = 0 to V

CC

-1 1 µA

I

OL

Output Leakage V

OUT

= GND to V

CC

-1 1 µA

V

IL

Input Low Voltage -0.3 VCC * 0.3 V

V

IH

Input High Voltage 0.7 * V

CC

VCC + 0.3 V

V

OL

Output Low Voltage IOL = 1.6 mA 0.4 V

V

OH

Output High Voltage IOH = -0.8 mA VCC - 0.8 V

f

OP

SCK Frequency 2.1 MHz

t

RI

Input Rise Time 2.0 µs

t

FI

Input Fall Time 2.0 µs

t

CLH

Clock High Time (Note 2) 190 ns

t

CLL

Clock Low Time (Note 2) 190 ns

t

CSH

Min CS High Time (Note 3) 240 ns

t

CSS

CS Setup Time 240 ns

t

DIS

Data Setup Time 100 ns

t

HDS

HOLD Setup Time 90 ns

t

CSN

CS Hold Time 240 ns

t

DIN

Data Hold Time 100 ns

t

HDN

HOLD Hold Time 90 ns

t

PD

Output Delay CL = 200 pF 240 ns

t

DH

Output Hold Time 0 ns

t

LZ

HOLD to Output Low Z 100 ns

t

DF

Output Disable Time CL = 200 pF 240 ns

t

HZ

HOLD to Output High Z 100 ns

t

WP

Write Cycle Time 1–4 Bytes 10 ms

Capacitance (Note 4) T

A

= 25°C, f = 2.1/1 MHz

Symbol Test Typ Max Units

C

OUT

Output Capacitance

38pF

C

IN

Input Capacitance 2 6 pF

AC Test Conditions

Output Load CL = 200 pF
Input Pulse Levels 0.1 * VCC - 0.9 * V

CC

Timing Measurement Reference Level 0.3 * VCC - 0.7 * V

CC

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t

CLH

+ t

CLL

must be equal to or greater than 1/fOP. For

example, if the 2.1MHz period = 476ns and t

CLH

= 190ns, t

CLL

must be 286ns.

Note 3: CS must be brought high for a minimum of t

CSH

between consecutive instruction cycles.

Note 4: This parameter is periodically sampled and not 100% tested.

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Absolute Maximum Ratings (Note 5)

Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltage with

Respect to Ground +6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.) +300°C
ESD Rating 2000V

Operating Conditions

Ambient Operating Temperature

NM25C041L/LZ 0°C to +70°C
NM25C041LE/LZE -40°C to +85°C
NM25C041LV -40°C to +125°C

Power Supply (VCC) 2.7V - 4.5V

DC and AC Electrical Characteristics 2.7V ≤ V

CC

≤ 4.5V

25C041L/LE 25C041LV

25C041LZ/LZE

Symbol Parameter Conditions Min. Max. Min Max Units

I

CC

Operating Current CS = V

IL

33mA

I

CCSB

Standby Current CS = V

CC

µA
L 10 10
LZ 1 N/A

I

IL

Input Leakage VIN = 0 to V

CC

-1 1 -1 1 µA

I

OL

Output Leakage V

OUT

= GND to V

CC

-1 1 -1 1 µA

V

IL

Input Low Voltage -0.3 VCC * 0.3 -0.3 VCC * 0.3 V

V

IH

Input High Voltage 0.7 * VCCVCC + 0.3 0.7 * VCCVCC + 0.3 V

V

OL

Output Low Voltage I

OL

= 0.8 mA 0.4 0.4 V

V

OH

Output High Voltage I

OH

= –0.8 mA VCC - 0.8 VCC - 0.8 V

f

OP

SCK Frequency 1.0 1.0 MHz

t

RI

Input Rise Time 2.0 2.0 µs

t

FI

Input Fall Time 2.0 2.0 µs

t

CLH

Clock High Time (Note 6) 410 410 ns

t

CLL

Clock Low Time (Note 6) 410 410 ns

t

CSH

Min. CS High Time (Note 7) 500 500 ns

t

CSS

CS Setup Time 500 500 ns

t

DIS

Data Setup Time 100 100 ns

t

HDS

HOLD Setup Time 240 240 ns

t

CSN

CS Hold Time 500 500 ns

t

DIN

Data Hold Time 100 100 ns

t

HDN

HOLD Hold Time 240 240 ns

t

PD

Output Delay 500 500 ns

t

DH

Output Hold Time 0 0 ns

t

LZ

HOLD Output Low Z 240 240 ns

t

DF

Output Disable Time 500 500 ns

t

HZ

HOLD to Output Hi Z 240 240 ns

t

WP

Write Cycle Time 1-4 Bytes 15 15 ms

Capacitance T

A

= 25°C, f = 2.1/1 MHz (Note 8)

Symbol Test Typ Max Units

C

OUT

Output Capacitance 3 8 pF

C

IN

Input Capacitance 2 6 pF

AC Test Conditions

Output Load CL = 200 pF
Input Pulse Levels 0.1 * VCC - 0.9 * V

CC

Timing Measurement Reference Level 0.3 * VCC - 0.7 * V

CC

Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 6 : The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t

CLH

+ t

CLL

must be equal to or greater than 1/fOP. For

example, if the 2.1MHz period = 476ns and t

CLH

= 190ns, t

CLL

must be 286ns.

Note 7: CS must be brought high for a minimum of t

CSH

between consecutive instruction cycles.

Note 8: This parameter is periodically sampled and not 100% tested.

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

AC Test Conditions (Continued)

FIGURE 1. Synchronous Data Timing

CS

SCK

SI

SO

HI-Z HI-Z

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

t

CSS

t

CSH

t

CSN

t

DIStDIN

t

DF

t

PD

t

PD

t

CLH

t

CLL

HOLD

SCK

SO

t

HZ

t

LZ

t

HDN

t

HDS

t

HDN

t

HDS

DS800002-4

DS800002-6

FIGURE 2. HOLD Timing

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Functional Description

TABLE 1. Op Codes Table

Instruction Instruction Operation

Name Opcode

WREN 0000 0110 Set Write Enable Latch

WRDI 0000 0100 Reset Write Enable Latch

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register

READ 0000 A011 Read Data from Memory

Array

WRITE 0000 A010 Write Data to Memory

Array

Note: As the NM25C040 requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29), the
9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This

convention only applies to 4K SPI protocol.

The NM25C041 SPI device uses a CS functionality, so the device
is selected when CS is LOW (CS is to be held HIGH during
'standby' periods and between instruction sets). As stated above,
the SPI protocol defines this as a MODE 1 part, with a CLOCK
PHASE 1 and CLOCK POLARITY 0. This means that the part is
active with CS = 0 (VIL), all INPUT data is latched into the device
on the RISING edge of SCK and all OUTPUT data is clocked out
on the FALLING edge of SCK.

FIGURE 3. SPI Protocol

…

…

…

CS

SCK

SI

SO

Bit 7 Bit 6

Bit 6

Bit 0Bit 1

Bit 7

Bit 0

Bit 1

The HOLD pin operation is used when the device is selected (CS
LOW) and the application requires that the SI datastream be
stopped and then restarted. The HOLD pin allows a fully 'static'
operation, wherin the device may be put on HOLD by bringing the
HOLD pin LOW (VIL). During the HOLD state, SCK must be HIGH
and CS must remain LOW (device selected). In order to resume
EEPROM serial communication, HOLD must be again brought
HIGH and the SCK/SI signals resumed. During the HOLD state,
SO is tri-stated (high impedance).

DS800002-5

As an additional protection against data corruption, the device is
designed so that, if an invalid opcode is received, the device will
not shift any further data into the SI latches and SO will remain tri­stated. In this case, CS must again be brought HIGH to re-initialize
the device and a new opcode re-entered. See Figure 4.

FIGURE 4. Invalid Op-Code

CS

SI

SO

INVALID OP-CODE

DS800002-7

CS

SI

SO

READ

OP-CODE

BYTE

ADDR (n)

DATA

(n)

DATA
(n+1)

DATA
(n+2)

DATA
(n+3)

DS800002-8

READ STATUS REGISTER (RDSR): The Read Status Register
(RDSR) instruction provides access to the status register which is
used to interrogate the READY/BUSY and WRITE ENABLE
status of the chip. Two non-volatile status register bits are used to
select one of four levels of BLOCK WRITE PROTECTION. The
status register format is shown in Table 2.

READ SEQUENCE: Reading the memory via the SPI link re­quires the following sequence. The CS line is pulled low to select
the device. The READ op-code (which includes A8) is transmitted
on the SI line followed by the byte address (A7–A0) to be read.
After this is done, data on the SI line becomes don’t care. The data
(D7–D0) at the address specified is then shifted out on the SO line.
If only one byte is to be read, the CS line can be pulled back to the
high level. It is possible to continue the READ sequence as the
byte address is automatically incremented and data will continue
to be shifted out. When the highest address is reached (1FF), the
address counter rolls over to lowest address (000) allowing the
entire memory to be read in one continuous READ cycle. See
Figure 5.

FIGURE 5. Read Sequence

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Functional Description (Continued)

TABLE 2. Status Register Format

Bit Bit Bit Bit Bit Bit Bit Bit

76543210

X X X X BP1 BP0 WEN RDY

X = Don't Care

Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec­tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed

during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 6.

TABLE 3. Block Write Protection Levels

Level Status Register Bits Array

Address

BP1 BP0 Protected

0 0 0 None
1 0 1 180–1FF
2 1 0 100–1FF
3 1 1 000–1FF

FIGURE 6. Read Status

WRITE ENABLE (WREN): When VCC is applied to the chip, it

“powers up” in the write disable state. Therefore, all modes must
be preceded by a WRITE ENABLE (WREN) instruction. Addition­ally the WP pin must be held high during a WRITE ENABLE
instruction. At the completion of a WRITE or WRSR cycle the
device is automatically turned to the write disable state. Note that
a WRITE DISABLE (WRDI) instruction or forcing the WP pin low
will also return the device to the write disable state. See Figure 7.

FIGURE 7. Write Enable

WRITE DISABLE (WRDI): To protect against accidental data

disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. The WRITE DISABLE instruction is inde­pendent of the status of the WP pin. See Figure 8.

FIGURE 8. Write Disable

CS

SCK

SI

SO

D2 D1 D0

DS800002-12

CS

SI

SO

RDSR

OP-CODE

SR_DATA
MSB...LSB

DS800002-9

CS

SI

SO

WREN OP-CODE

DS800002-10

CS

SI

SO

WRDI OP-CODE

DS800002-11

WRITE SEQUENCE: To program the device the WRITE PRO­TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.

A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code (which
includes A8) is transmitted on the SI line followed by the byte
address (A7–A0) and the corresponding pro-data (D7–D0) to be
programmed. Programming will start after the CS pin is forced
back to a high level. Note that the LOW to HIGH transition of the
CS pin must occur during the SCK low time immediately after
clocking in the D0 data bit. The READY/BUSY status of the device
can be determined by executing a READ STATUS REGISTER
(RDSR) instruction. Bit 0 = 1 indicates that the WRITE cycle is still
in progress and Bit 0 = 0 indicates that the WRITE cycle has
ended. During the WRITE programming cycle (Bit 0 = 1) only the
READ STATUS REGISTER instruction is enabled.

FIGURE 9. Start WRITE Condition

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Functional Description (Continued)

The NM25C041 is capable of a four byte PAGE WRITE operation.
After receipt of each byte of data the two low order address bits are
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
than four bytes of data, the address counter will “roll over”, and the
previously loaded data will be reloaded. See Figure 10.

FIGURE 10. 4 Page Byte Write

At the completion of a WRITE cycle the device is automatically
returned to the write disable state.

If the WP pin is forced low or the device is not WRITE enabled, the
device will ignore the WRITE instruction and return to the standby
state when CS is forced high. A new CS falling edge is required to
re-initialize the serial communication.

WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non­volatile status register Bits 2 and 3 (BP0 and BP1). As in the
WRITE mode the WRITE PROTECT (WP) pin must be held high
and two separate instructions must be executed. The chip must
first be write enabled via the WRITE ENABLE instruction and then
a WRSR instruction must be executed.

The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be programmed
(see Figure 11).

FIGURE 11. Write Status Register

Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
during the SCK low time immediately after clocking in the last don’t
care bit. See Figure 12.

FIGURE 12. Start WRSR Condition

CS

SCK

SI

SO

BP0

t

DIN

t

CSN

t

DIS

DS800002-15

CS

SI

SO

DATA
(n+3)

DATA
(n+2)

DATA
(n+1)

DATA

(n)

BYTE

ADDR(n)

WRITE

OP-CODE

DS800002-13

CS

SI

SO

WRSR

OP-CODE

SR_DATA

XXXXBP1BP0XX

DS800002-14

The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.

At the completion of a WRSR cycle the device is automatically
returned to the write disable state.

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Molded Small Out-Line Package (M8)

Order Number NM25C041M8

Package Number M08A

Physical Dimensions inches (millimeters) unless otherwise noted

1234

8765

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

Seating

Plane

0.004 - 0.010

(0.102 - 0.254)

0.014 - 0.020

(0.356 - 0.508)

0.014

(0.356)

Typ.

0.053 - 0.069

(1.346 - 1.753)

0.050

(1.270)

Typ

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

8° Max, Typ.

All leads

0.150 - 0.157

(3.810 - 3.988)

0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads

0.04

(0.102)

All lead tips

0.010 - 0.020

(0.254 - 0.508)

x 45°

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Physical Dimensions inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N)

Order Number NM25C041N

Package Number N08E

0.373 - 0.400

(9.474 - 10.16)

0.092

(2.337)

DIA

+

1234

8765

0.250 - 0.005

(6.35 ± 0.127)

87

0.032 ± 0.005

(0.813 ± 0.127)

Pin #1

Option 2

RAD

1

0.145 - 0.200

(3.683 - 5.080)

0.130 ± 0.005

(3.302 ± 0.127)

0.125 - 0.140

(3.175 - 3.556)

0.020

(0.508)

Min

0.018 ± 0.003

(0.457 ± 0.076)

90° ± 4°

Typ

0.100 ± 0.010

(2.540 ± 0.254)

0.040

(1.016)

0.039

(0.991)

Typ.

20° ± 1°

0.065

(1.651)

0.050

(1.270)

0.060

(1.524)

Pin #1 IDENT

Option 1

0.280

MIN

0.300 - 0.320
(7.62 - 8.128)

0.030

(0.762)

MAX

0.125

(3.175)

DIA

NOM

0.009 - 0.015

(0.229 - 0.381)

0.045 ± 0.015

(1.143 ± 0.381)

0.325

+0.040

-0.015

8.255

+1.016

-0.381

95° ± 5°

0.090

(2.286)

(7.112)

IDENT

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex­pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.

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