Datasheet NM24C65LEM8X, NM24C65LEN, NM24C65N, NM24C65XLZEM8, NM24C65XLZM8X Datasheet (Fairchild Semiconductor)

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

PRELIMINARY

March 1999

© 1999 Fairchild Semiconductor Corporation

NM24C65
64K-Bit Extended 2-Wire Bus Interface
Serial EEPROM with Write Protect

General Description:

The NM24C65 devices are 65,536 bits of CMOS nonvolatile
electrically erasable memory. These devices offer the designer
different low voltage and low power options, and they conform to
all in the Extended IIC 2-wire protocol. Furthermore, they are
designed to minimize device pin count and simplify PC board
layout requirements.

The upper half of the memory can be disabled (Write Protection)
by connecting the WP pin to VCC. This section of memory then
becomes ROM.

This communication protocol uses CLOCK (SCL) and DATA I/O
(SDA) lines to synchronously clock data between the master (for
example a microprocessor) and the slave EEPROM device(s).

Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con­sumption.

Block Diagram

Features:

■ Extended operating voltage 2.7V – 5.5V

■ 400 KHz clock frequency (F) at 2.7V - 5.5V

■ 200µA active current typical

10µA standby current typical
1µA standby typical (L)

0.1µA standby typical (LZ)

■ IIC compatible interface
– Provides bidirectional data transfer protocol

■ 32 byte page write mode
– Minimizes total write time per byte

■ Self timed write cycle
Typical write cycle time of 6ms

■ Hardware write protect for upper block

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin SO, 8-pin DIP

■ Low VCC programming lockout (3.8V - on Standard V

CC

devices only).

DS500042-1

H.V. GENERATION

TIMING &CONTROL

E2PROM

ARRAY

YDEC

DATA REGISTER

XDEC

CONTROL

LOGIC

WORD
ADDRESS
COUNTER

SLAVE ADDRESS

REGISTER &

COMPARATOR

START

STOP

LOGIC

WRITE

LOCKOUT

START CYCLE

CK

D

IN

R/W

LOAD INC

SDA

SCL

WP

V

CC

D

OUT

A2
A1
A0

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

Top View

See Package Number N08E and M08A

Pin Names

A0, A1, A2 Device Address Input

V

SS

Ground
SDA Data I/O
SCL Clock Input

WP Write Protect
V

CC

Power Supply

Ordering Information
NM 24 C XX F LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SO8

Temp. Range None 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 4.5V
LZ 2.7V to 4.5V and

<1µA Standby Current

SCL Clock Frequency Blank 100KHz

F 400KHz

Density 65 64K with Write Protect

C CMOS

Interface 24 IIC

NM Fairchild Non-Volatile

Memory

A0
A1
A2

V

SS

V

CC

WP
SCL
SDA

8
7
6
5

1
2
3
4

NM24C65

DS500042-2

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Product Specifications
Absolute Maximum Ratings

Ambient Storage Temperature –65°C to +150°C
All Input or Output Voltages

with Respect to Ground 6.5V to –0.3V

Lead Temperature

(Soldering, 10 seconds) +300°C

ESD Rating 2000V min.

Operating Conditions

Ambient Operating Temperature

NM24C65 0°C to +70°C
NM24C65E -40°C to +85°C
NM24C65V -40°C to +125°C

Positive Power Supply

NM24C65 4.5V to 5.5V
NM24C65L 2.7V to 4.5V
NM24C65LZ 2.7V to 4.5V

Standard VCC (4.5V to 5.5V) DC Electrical Characteristics

Symbol Parameter Test Conditions Limits Units

Min

Typ (Note 1)

Max

I

CCA

Active Power Supply Current f

SCL

= 100 KHz 0.2 1.0 mA

I

SB

Standby Current VIN = GND or V

CC

10 50 µA

I

LI

Input Leakage Current VIN = GND to V

CC

0.1 1 µA

I

LO

Output Leakage Current V

OUT

= GND to V

CC

0.1 1 µA

V

IL

Input Low Voltage –0.3 VCC x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output Low Voltage I

OL

= 3 mA 0.4 V

Low VCC (2.7V to 4.5V) DC Electrical Characteristics

Symbol Parameter Test Conditions Limits Units

Min

Typ (Note 1)

Max

I

CCA

Active Power Supply Current f

SCL

= 100 kHz 0.2 1.0 mA

I

SB

Standby Current for L VIN = GND or V

CC

110µA

(Note 1) Standby Current for LZ VIN = GND or V

CC

0.1 1 µA

I

LI

Input Leakage Current VIN = GND to V

CC

0.1 1 µA

I

LO

Output Leakage Current V

OUT

= GND to V

CC

0.1 1 µA

V

IL

Input Low Voltage –0.3 V

CC

x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output Low Voltage IOL = 3 mA 0.4 V

Capacitance T

A

= +25°C, f = 100/400 KHz, VCC = 5V (Note 2)

Symbol Test Conditions Max Units

C

I/O

Input/Output Capacitance (SDA) V

I/O

= 0V 8 pF

C

IN

Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF

Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

AC Conditions of Test

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels VCC x 0.5
Output Load 1 TTL Gate and CL = 100 pF

Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)

Symbol Parameter 100 KHz 400 KHz Units

Min Max Min Max

f

SCL

SCL Clock Frequency 100 400 KHz

T

I

Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V

IN

100 50 ns

Pulse width)

t

AA

SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs

t

BUF

Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start

t

HD:STA

Start Condition Hold Time 4.0 0.6 µs

t

LOW

Clock Low Period 4.7 1.5 µs

t

HIGH

Clock High Period 4.0 0.6 µs

t

SU:STA

Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)

t

HD:DAT

Data in Hold Time 0 0 ns

t

SU:DAT

Data in Setup Time 250 100 ns

t

R

SDA and SCL Rise Time 1 0.3 µs

t

F

SDA and SCL Fall Time 300 300 ns

t

SU:STO

Stop Condition Setup Time 4.7 0.6 µs

t

DH

Data Out Hold Time 300 50 ns

t

WR

Write Cycle Time - NM24C65 10 10 ms

(Note 3) - NM24C65L, NM24C65LZ 15 15

Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C65 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

BACKGROUND INFORMATION (IIC Bus)

As mentioned, the IIC bus allows synchronous bidirectional commu­nication between Transmitter/Receiver using the SCL (clock) and
SDA (Data I/O) lines. All communication must be started with a valid
START condition, concluded with a STOP condition and acknowl­edged by the Receiver with an ACKNOWLEDGE condition.

In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
slave address, must follow the START condition. For EEPROMs,
the first 4-bits of the slave address is '1010'. This is then followed
by the device selection bits A2, A1 and A0.The final bit in the slave
address determines the type of operation performed (READ/
WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The
slave address is then followed by two bytes that define the word
address, which is then followed by the data byte.

The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
4M bits in the Extended IIC protocol. EEPROM memory address­ing is controlled by hardware configuring the A2, A1, and A0 pins
(Device Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to VSS).

Addressing an EEPROM memory location involves sending a
command string with the following information:

[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD­DRESS]-[BYTE ADDRESS]

Definitions

Word 8 bits (byte) of data
Page 32 sequential addresses (one byte each) that

may be programmed during a "Page Write"
programming cycle.

Master Any IIC device CONTROLLING the transfer

of data (such as a microcontroller).

Slave Device being controlled (EEPROMS are

always considered Slaves).

Transmitter Device currently SENDING data on the bus

(may be either a Master or Slave).

Receiver Device currently receiving data on the bus

(Master or Slave).

Pin Description

SERIAL CLOCK (SCL)

The SCL input is used to clock all data into and out of the device.

SERIAL DATA (SDA)

SDA is a biderectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.

Device Address Inputs (A0, A1, A2)

Device address pins A0, A1, and A2 are connected to VCC or VSS to
configure the EEPROM address for multiple device configuration. A
total of eight different devices can be attached to the same SDA bus.

Write Protection (WP)

If WP is tied to VCC, program WRITE operations onto the upper half
of the memory will not be executed. READ operations are always
available.

If WP is tied to VSS, normal memory operation is enabled, READ/
WRITE over the entire bit memory array.

This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.

Device Operation

The NM24C65xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is controlled
is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. There­fore, the NM24C65xxx is considered a slave in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and reserved for indicating
start and stop conditions.

Refer to Figures 2 and 3.

START CONDITION

All commands are preceded by the start condition, which is a HIGH to
LOW transition of SDA when SCL is HIGH. The NM24C65xxx
continuously monitors the SDA and SCL lines for the start condition and
will not respond to any command until this condition has been met.

STOP CONDITION

All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C65xxx to place the device in
the standby power mode.

SCL

SDA

IN

SDA

OUT

t

F

t

LOW

t

HIGH

t

R

t

LOW

t

AA

t

DH

t

BUF

t

SU:STA

t

HD:DAT

t

HD:STA

t

SU:DAT

t

SU:STO

DS500042-3

Bus Timing

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Write Cycle Timing

ACKNOWLEDGE

Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits. During the ninth clock
cycle the receiver will pull the SDA line LOW to acknowledge that
it received the eight bits of data. Refer to

Figure 4

.

The NM24C65xxx device will always respond with an acknowl­edge after recognition of a start condition and its slave address. If

Write Cycle Timing (Figure 1)

SDA

SCL

STOP

CONDITION

START

CONDITION

WORD n

8th BIT ACK

t

WR

SDA

SCL

DATA STABLE

DATA

CHANGE

SDA

SCL

START

BIT

STOP

BIT

DS500042-4

DS500042-5

Data Validity (Figure 2)

Definition of Start and Stop (Figure 3)

DS500042-6

both the device and a WRITE operation have been selected, the
NM24C65xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.

In the READ mode the NM24C65xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl­edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.

SCL FROM

MASTER

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

189

Acknowledge Response from Receiver (Figure 4)

DS500042-7

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

S
T
O
P

A
C
K

Bus Activity:

Master

SDA Line

1010 000

Bus Activity

A
C
K

DATA

A
C
K

A
C
K

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

S
T
A
R
T

DEVICE ADDRESSING

Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all EEPROM devices.

The next three bits identifies the device address. Address from
000 to 111 are acceptable thus allowing up to eight devices to be
connected to the IIC bus.

The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the NM24C65xxx recognizes the start
condition, the devices interfaced to the IIC bus waits for a slave
address to be transmitted over the SDA line. If the transitted slave
address matches an address of one of the devices, the designated
slave pulls the line LOW with an acknowledge. signal and awaits
further transmissions.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address bytes, with 13
active bits, are required after the SLAVE acknowledge to address
the full memory array. The first byte indicates the high-order byte
of the word address. Only the five least signicant bits can be
changed, the other bits are pre-assigned the value "0". Following
the acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the NM24C65xxx responds with another ac­knowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the

NM24C65xxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer to

Figure 5

for the address, acknowledge

and data transfer sequence.

PAGE WRITE

The NM24C65xxx is capable of thirty-two byte page write opera­tion. It is initiated in the same manner as the byte write operation;
but instead of termination the write cycle after the first data word
is transfered, the master can transmit up to thirty-one more words.
After the receipt of each word, the device responds with an
acknowledge.

After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is ac­cepted. If the master should transmit more than thirty-two words
prior to generating the stop condition, the address counter will "roll
over" and the previous written data will be overwritten. As with the
byte write operation, all inputs are disabled until completion of the
internal write cycle. Refer to

Figure 6

for the address, acknowl-

edge and data transfer sequence.

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's
write operation, the NM24C65xxx initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the NM24C65xxx is still busy with the write operation, no ACK
will be returned. If the device has completed the write operation,
an ACK will be returned and the host can then proceed with the
next read or write operation.

DS500042-8

Byte Write (Figure 5)

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Write Protection

Programming of the upper half of memory will not take place if the
WP pin is connected to VCC. The device will accept slave and word
addresses; but if the memory accessed is write protected by the
WP pin, the NM24C65xxx will not generate an acknowledge after
the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.

Low VCC Lockout

NM24C65xxx provides data security against inadvertent writes
that could potentially happen during the time the device is being
powered on, powered down and brown out conditions by monitor­ing the VCC voltage during a write cycle. Whenever a write cycle
is started, the built-in circuitry starts to monitor the VCC level
throughout the duration of the write command sequence until the
master issues the required STOP condition to start the actual
internal write operation. If the sensed VCC voltage is below 3.8V at
any point during this monitoring period, the device prohibits the
write operation and does not generate the ACK pulse. This low
VCC lockout feature is only available for standard 5V device.

Read Operation

Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.

CURRENT ADDRESS READ

Internally the NM24C65xxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
one, the NM24C65xxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge acknowledge the
transfer but does generate a stop condition, and therefore discon-

tinues transmission. Refer to

Figure 7

for the sequence of ad-

dress, acknowledge and data transfer.

RANDOM READ

Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, slave address
and then the word address it is to read. After the word address
acknowledge, the master immediately reissues the start condition
and the slave address with the R/W bit set to "1". This will be
followed by an acknowledge from the NM24C65xxx and then by
the eight bit word. The master will not acknowledge the transfer
but does generate the stop condition, and therefore the
NM24C65xxx discontinues transmission. Refer to

Figure 8

for the

address, acknowledge and data transfer sequence.

SEQUENTIAL READ

Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C65xxx continues to output data for each ac­knowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.

The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
NM24C65xxx continues to output data for each acknowledge
received. Refer to

Figure 9

for the address, acknowledge and data

transfer sequence.

S
T
O
P

A
C
K

A
C
K

Bus Activity:

Master

SDA Line

1010 000

Bus Activity

A
C
K

DATA n DATA n+31

A
C
K

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

S
T
A
R
T

DS500042-9

Page Write (Figure 6)

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Current Address Read (Figure 7)

Random Read (Figure 8)

Sequential Read (Figure 9)

S

T
O
P

A
C
K

NO

A
C
K

Bus Activity:

Master

SDA Line

1010

Bus Activity

A
C
K

DATA n + x

A
C
K

DATA n + 1DATA n

SLAVE

ADDRESS

A
C
K

S
T
A
R
T

S
T
O
P

A
C
K

NO

A
C
K

Bus Activity:

Master

SDA Line

1010 101010000

Bus Activity

A
C
K

A
C
K

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

SLAVE

ADDRESS

DATA n

A

C

K

S

T
A
R

T

S
T
A
R
T

S

T
O
P

A
C
K

NO

A
C
K

1010

DATASLAVE ADDRESS

S
T
A
R
T

DS500042-10

DS500042-11

DS500042-12

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Molded Small Out-Line Package (M8)

Order Number NM24C65xxxM8 or NM24C65xxxEM8

Package Number M08A

Physical Dimensions inches (millimeters) unless otherwise noted

1234

8765

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

Seating

Plane

0.004 - 0.010

(0.102 - 0.254)

0.014 - 0.020

(0.356 - 0.508)

0.014

(0.356)

Typ.

0.053 - 0.069

(1.346 - 1.753)

0.050

(1.270)

Typ

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

8° Max, Typ.

All leads

0.150 - 0.157

(3.810 - 3.988)

0.0075 - 0.0098
(0.190 - 0.249)

Typ. All Leads

0.04

(0.102)

All lead tips

0.010 - 0.020

(0.254 - 0.508)

x 45°

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NM24C65 Rev. C.3

NM24C65 64K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

Physical Dimensions inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N)

Order Number NM24C65xxxN or NM24C65xxxEN

Package Number N08E

0.373 - 0.400

(9.474 - 10.16)

0.092

(2.337)

DIA

+

1234

8765

0.250 - 0.005

(6.35 ± 0.127)

87

0.032 ± 0.005

(0.813 ± 0.127)

Pin #1

Option 2

RAD

1

0.145 - 0.200

(3.683 - 5.080)

0.130 ± 0.005

(3.302 ± 0.127)

0.125 - 0.140

(3.175 - 3.556)

0.020

(0.508)

Min

0.018 ± 0.003

(0.457 ± 0.076)

90° ± 4°

Typ

0.100 ± 0.010

(2.540 ± 0.254)

0.040

(1.016)

0.039

(0.991)

Typ.

20° ± 1°

0.065

(1.651)

0.050

(1.270)

0.060

(1.524)

Pin #1 IDENT

Option 1

0.280

MIN

0.300 - 0.320
(7.62 - 8.128)

0.030

(0.762)

MAX

0.125

(3.175)

DIA

NOM

0.009 - 0.015

(0.229 - 0.381)

0.045 ± 0.015

(1.143 ± 0.381)

0.325

+0.040

-0.015

8.255

+1.016

-0.381

95° ± 5°

0.090

(2.286)

(7.112)

IDENT

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex­pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.

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Tel. [phone] Deutsch Tel: [phone] Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku

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Français Tel: [phone] Tel; [phone] Tel: [phone]
Italiano Tel: [phone] Fax: [phone] Fax: [phone]