Datasheet NM24C04UEN, NM24C04UFEM8, NM24C04UFLM8, NM24C04UM8X, NM24C04UMT8 Datasheet (Fairchild Semiconductor)

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

August 1999

© 1999 Fairchild Semiconductor Corporation

NM24C04U/NM24C05U
4K-Bit Serial EEPROM
2-Wire Bus Interface

General Description

The NM24C04U/05U devices are 4K (4,096) bit serial interface
CMOS EEPROMs (Electrically Erasable Programmable Read­Only Memory). These devices fully conform to the Standard I2C™
2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins
to synchronously clock data between the "master" (for example a
microprocessor) and the "slave" (the EEPROM device). In addi­tion, the serial interface allows a minimal pin count packaging
designed to simplify PC board layout requirements and offers the
designer a variety of low voltage and low power options.

NM24C05U incorporates a hardware "Write Protect" feature, by
which, the upper half of the memory can be disabled against
programming by connecting the WP pin to VCC. This section of
memory then effectively becomes a ROM (Read-Only Memory)
and can no longer be programmed as long as WP pin is connected
to VCC.

Fairchild EEPROMs are designed and tested for applications requir­ing high endurance, high reliability and low power consumption for a
continuously reliable non-volatile solution for all markets.

Block Diagram

Functions

■ I2C™ compatible interface

■ 4,096 bits organized as 512 x 8

■ Extended 2.7V – 5.5V operating voltage

■ 100 KHz or 400 KHz operation

■ Self timed programming cycle (6ms typical)

■ "Programming complete" indicated by ACK polling

■ NM24C05U: Memory "Upper Block" Write Protect pin

Features

■ The I2C™ interface allows the smallest I/O pincount of any
EEPROM interface

■ 16 byte page write mode to minimize total write time per byte

■ Typical 200µA active current (I

CCA

)

■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices

■ Endurance: Up to 1,000,000 data changes

■ Data retention greater than 40 years

H.V. GENERATION

TIMING &CONTROL

E2PROM

ARRAY

YDEC

DATA REGISTER

XDEC

CONTROL

LOGIC

WORD
ADDRESS
COUNTER

SLAVE ADDRESS

REGISTER &

COMPARATOR

START

STOP

LOGIC

CK

D

IN

R/W

SDA

SCL

V

SS

WP

V

CC

D

OUT

A2
A1

DS800008-1

I2C™ is a registered trademark of Philips Electronics N.V.

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

NC

A1
A2

V

SS

V

CC

NC
SCL
SDA

8
7
6
5

1
2
3
4

Connection Diagrams

Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8)

Top View

See Package Number N08E, M08A, and MTC08

Pin Names

A1,A2 Device Address Inputs

V

SS

Ground
SDA Serial Data I/O
SCL Serial Clock Input

NC No Connection
V

CC

Power Supply

Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8)

Top View

See Package Number N08E, M08A, and MTC08

Pin Names

NC No Connection

A1,A2 Device Address Inputs

V

SS

Ground
SDA Serial Data I/O
SCL Serial Clock input

WP Write Protect
V

CC

Power Supply

NC

A1
A2

V

SS

V

CC

WP
SCL
SDA

8
7
6
5

1
2
3
4

NM24C04U

NM24C05U

DS800008-2

DS800008-3

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Ordering Information

NM 24 C XX U F LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SOIC
MT8 8-pin TSSOP

Temp. Range None 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 5.5V
LZ 2.7V to 5.5V and

<1µA Standby Current

SCL Clock Frequency Blank 100KHz

F 400KHz

Ultralite CS100UL Process

Density 04 4K

05 4K with Write Protect

C CMOS Technology
W Total Array Write Protect

Interface 24 IIC

NM Fairchild Non-Volatile

Memory

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Product Specifications

Absolute Maximum Ratings

Ambient Storage Temperature –65°C to +150°C
All Input or Output Voltages

with Respect to Ground 6.5V to –0.3V

Lead Temperature

(Soldering, 10 seconds) +300°C

ESD Rating 2000V min.

Operating Conditions

Ambient Operating Temperature

NM24C04U/05U 0°C to +70°C
NM24C04UE/05UE -40°C to +85°C
NM24C04UV/05UV -40°C to +125°C

Positive Power Supply

NM24C04U/05U 4.5V to 5.5V
NM24C04UL/05UL 2.7V to 5.5V
NM24C04ULZ/05ULZ 2.7V to 5.5V

Standard VCC (4.5V to 5.5V) DC Electrical Characteristics

Symbol Parameter Test Conditions Limits Units

Min Typ Max

(Note 1)

I

CCA

Active Power Supply Current f

SCL

= 400 KHz 0.2 1.0 mA

f

SCL

= 100 KHz

I

SB

Standby Current VIN = GND or V

CC

10 50 µA

I

LI

Input Leakage Current VIN = GND to V

CC

0.1 1 µA

I

LO

Output Leakage Current V

OUT

= GND to V

CC

0.1 1 µA

V

IL

Input Low Voltage –0.3 VCC x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output Low Voltage I

OL

= 3 mA 0.4 V

Low VCC (2.7V to 5.5V) DC Electrical Characteristics

Symbol Parameter Test Conditions Limits Units

Min Typ Max

(Note 1)

I

CCA

Active Power Supply Current f

SCL

= 400 KHz 0.2 1.0 mA

f

SCL

= 100 KHz

I

SB

Standby Current VIN = GND VCC = 2.7V - 4.5V 1 10 µA

or V

CC

VCC = 2.7V - 4.5V 0.1 1 µA
VCC = 4.5V - 5.5V 10 50 µA

I

LI

Input Leakage Current VIN = GND to V

CC

0.1 1 µA

I

LO

Output Leakage Current V

OUT

= GND to V

CC

0.1 1 µA

V

IL

Input Low Voltage –0.3 V

CC

x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output Low Voltage IOL = 3 mA 0.4 V

Capacitance T

A

= +25°C, f = 100/400 KHz, VCC = 5V (Note 2)

Symbol Test Conditions Max Units

C

I/O

Input/Output Capacitance (SDA) V

I/O

= 0V 8 pF

C

IN

Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF

Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

AC Conditions of Test

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels VCC x 0.5
Output Load 1 TTL Gate and CL = 100 pF

Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)

Symbol Parameter 100 KHz 400 KHz Units

Min Max Min Max

f

SCL

SCL Clock Frequency 100 400 KHz

T

I

Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V

IN

100 50 ns

Pulse width)

t

AA

SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs

t

BUF

Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start

t

HD:STA

Start Condition Hold Time 4.0 0.6 µs

t

LOW

Clock Low Period 4.7 1.5 µs

t

HIGH

Clock High Period 4.0 0.6 µs

t

SU:STA

Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)

t

HD:DAT

Data in Hold Time 0 0 µs

t

SU:DAT

Data in Setup Time 250 100 ns

t

R

SDA and SCL Rise Time 1 0.3 µs

t

F

SDA and SCL Fall Time 300 300 ns

t

SU:STO

Stop Condition Setup Time 4.7 0.6 µs

t

DH

Data Out Hold Time 300 50 ns

t

WR

Write Cycle Time - NM24C04U/05U 10 10 ms

(Note 3) - NM24C04U/05UL, NM24C04U/05ULZ 15 15

Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

SDA

SCL

Master

Transmitter/

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Slave

Receiver

Master

Transmitter/

Receiver

V

CC

V

CC

SDA

SCL

NM24C02U/03U

V

CC

V

CC

A0 A1 A2 V

SS

NM24C02U/03U

A0 A1 A2 V

SS

NM24C04U/05U

A1 A2 V

SS

NM24C08U/09U

A2 V

SS

V

CC

To V

CC

or V

SS

To V

CC

or V

SS

To V

CC

or V

SS

To V

CC

or V

SS

V

CC

V

CC

V

CC

Bus Timing

System Layout

Typical System Configuration

Note: Due to open drain configuration of SDA, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)

Example of 16K of Memory on 2-Wire Bus

Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.

The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF

Device Address Pins Memory Size # of Page

A0 A1 A2 Blocks

NM24C04U/05U No Connect ADR ADR 4096 Bits 2

DS800008-8

DS800008-20

DS800008-9

SCL

SDA

IN

SDA

OUT

t

F

t

LOW

t

HIGH

t

R

t

LOW

t

AA

t

DH

t

BUF

t

SU:STA

t

HD:DAT

t

HD:STA

t

SU:DAT

t

SU:STO

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Device Operation Inputs (A1, A2)

Device address pins A1 and A2 are connected to V

CC

or V

SS

to configure the EEPROM chip address. Table I shows the
active pins.

Table 1.

Device A0 A1 A2 Effects of Addresses

NM24C04U/05U x ADR ADR 22 = 4; 4*x (2x2K)** = 16K

* Max # of devices on bus ** Number of page blocks per density

Under the Standard IIC protocol the maximum density address­able using the three pin configuration of the IIC protocol is 16K.
Any combination of densities can be used up to this limit.

Background Information (IIC Bus)

As mentioned, the IIC bus allows synchronous bidirectional com­munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi­tion.

As shown below, the EEPROMs on the IIC bus may be configured
in any manner required, the total memory addressed can not
exceed 16K (16,384 bits). EEPROM memory address program­ming is controlled by 2 methods:

• Hardware configuring the A1 and A2 pins (Device Address
pins) with pull-up or pull-down to V

CC

or VSS. All unused

pins must be grounded (tied to VSS).

• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).

For devices with densities greater than 16K, a different protocol,
the Extended IIC protocol, is used. Refer to NM24C32U datasheet
(for example) for additional details.

Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]–[DEVICE ADDRESS]–[PAGE BLOCK AD­DRESS]–[BYTE ADDRESS]

DEFINITIONS

WORD 8 bits (byte) of data
PAGE 16 sequential addresses (one byte

each) that may be programmed
during a 'Page Write' programming
cycle

PAGE BLOCK 2048 (2K) bits organized into 16

pages of addressable memory.
(8 bits) x (16 bytes) x (16 pages)
= 2048 bits

MASTER Any IIC device CONTROLLING the

transfer of data (such as a
microprocessor)

SLAVE Device being controlled

(EEPROMs are always considered
Slaves)

TRANSMITTER Device currently SENDING data on

the bus (may be either a Master or
Slave).

RECEIVER Device currently RECEIVING data

on the bus (Master or Slave)

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.

WP Write Protection (NM24C05U Only)

If tied to VCC, PROGRAM operations onto the upper half of the
memory will not be executed. READ operations are possible. If
tied to V

SS

, normal operation is enabled, READ/WRITE over the

entire memory is possible.
This feature allows the user to assign the upper half of the memory

as ROM which can be protected against accidental programming.
When write is disabled, slave address and word address will be
acknowledged but data will not be acknowledged.

Device Operation

The NM24C04U/05U supports a bidirectional bus oriented proto­col. The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24C04U/05U will be considered a
slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to

Figure 2

and

Figure 3

on next

page.

Start Condition

All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
NM24C04U/05U continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.

Stop Condition

All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C04U/05U to place the device
in the standby power mode.

Write Cycle Timing

Acknowledge

Acknowledge is a hardware convention used to indicate success­ful data transfers. The transmitting device, either master or slave,
will release the bus after transmitting eight bits.

During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to

Figure 4.

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

DS800008-10

SDA

SCL

STOP

CONDITION

START

CONDITION

WORD n

8th BIT ACK

t

WR

Write Cycle Timing (Figure 1)

Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

Data Validity (Figure 2)

Start and Stop Definition (Figure 3)

Acknowledge Response from Receiver (Figure 4)

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

189

START

ACKNOWLEDGE

SDA

SCL

START

CONDITION

STOP

CONDITION

SCL

DATA STABLE DATA

CHANGE

SDA

DS800008-11

DS800008-12

DS800008-13

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Device Type

Identifier

Device

Address

1 0 1 0 A2 A1 A0 R/W (LSB)

NM24C04U/05U

Page

Block Address

DS800008-14

Write Cycle Timing (Continued)

The NM24C04U/05U device will always respond with an acknowl­edge after recognition of a start condition and its slave address. If
both the device and a write operation have been selected, the
NM24C04U/05U will respond with an acknowledge after the
receipt of each subsequent eight bit byte.

In the read mode the NM24C04U/05U slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl­edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.

Device Addressing

Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (

see Figure 5)

. This

is fixed as 1010 for all EEPROM devices.

Slave Addresses (Figure 5)

Refer to the following table for Slave Addresses string details:

Device A0 A1 A2 Page Page Block

Blocks Addresses

NM24C04U/05U P A A 2 00 01

A: Refers to a hardware configured Device Address pin
P: Refers to an internal PAGE BLOCK memory segment.

All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Word addressess 0000 through 1111).
Therefore, address bits A0, A1, or A2 (if designated 'P') are used
to access a PAGE BLOCK in conjunction with the Word address
used to access any individual data byte (Word).

The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.

A simple review: After the NM24C04U/05U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the line LOW with an acknowledge signal
and awaits further transmissions.

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Write Operations

BYTE WRITE

For a write operation a second address field is required which is
a word address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page of memory. Upon
receipt of the byte address the NM24C04U/05U responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
NM24C04U/05U begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
NM24C04U/05U inputs are disabled, and the device will not
respond to any requests from the master. Refer to

Figure 6

for the

address, acknowledge and data transfer sequence.

PAGE WRITE

The NM24C04U/05U is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to fifteen more
bytes. After the receipt of each byte, the NM24C04U/05U will
respond with an acknowledge.

After the receipt of each byte, the internal address counter
increments to the next address and the next SDA data is accepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will "roll over"
and the previously written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to

Figure 7

for the address, acknowl-

edge, and data transfer sequence.

S
T
O
P

Bus Activity:

Master

SDA Line

Bus Activity:

NM24C04U/05U

DATA n + 15

DATA n + 1DATA nWORD ADDRESS (n)

A
C
K

S
T
A
R
T

SLAVE

ADDRESS

A
C
K

A
C
K

A
C
K

A
C
K

S
T

O

P

A
C
K

DATA

A
C
K

A
C
K

S

T
A
R

T

WORD

ADDRESS

SLAVE

ADDRESS

Bus Activity:
Master

SDA Line

Bus Activity:
NM24C04U/05U

DS800008-15

DS800008-16

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s
write operation the NM24C04U/05U initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the NM24C04U/05U is still busy with the write
operation no ACK will be returned. If the NM24C04U/05U has
completed the write operation an ACK will be returned and the
host can then proceed with the next read or write operation.

Write Protection (NM24C05U Only)

Programming of the upper half of the memory will not take place
if the WP pin of the NM24C05U is connected to V

CC

. The
NM24C05U will accept slave and byte addresses; but if the
memory accessed is write protected by the WP pin, the NM24C05U
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted.

Byte Write (Figure 6)

Page Write (Figure 7)

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

S

T
O
P

A
C
K

NO

A
C
K

SLAVE

ADDRESS

A

C

K

A

C

K

S
T
A
R
T

S
T
A
R
T

WORD

ADDRESS

SLAVE

ADDRESS

Bus Activity:
Master

SDA Line

Bus Activity:
NM24C04U/05U

DATA n

S

T
O
P

A

C

K

Bus Activity:

Master

SDA Line

Bus Activity:

NM24C04U/05U

A
C
K

DATA n + x

A
C
K

DATA n + 2DATA n +1DATA n +1

A
C
K

NO

A
C
K

Slave

Address

DS800008-18

DS800008-19

Read Operations

Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.

Current Address Read

Internally the NM24C04U/05U contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the NM24C04U/05U issues an acknowledge and transmits
the eight bit byte. The master will not acknowledge the transfer
but does generate a stop condition, and therefore the NM24C04U/
05U discontinues transmission. Refer to

Figure 8

for the se-

quence of address, acknowledge and data transfer.

Random Read

Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address and then the byte address it is to read. After the
byte address acknowledge, the master immediately reissues the

start condition and the slave address with the R/W bit set to one.
This will be followed by an acknowledge from the NM24C04U/05U
and then by the eight bit data. The master will not acknowledge the
transfer but does generate the stop condition, and therefore the
NM24C04U/05U discontinues transmission. Refer to

Figure 9

for

the address, acknowledge and data transfer sequence.

Sequential Read

Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C04U/05U continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.

The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" and the
NM24C04U/05U continues to output data for each acknowledge
received. Refer to

Figure 10

for the address, acknowledge, and

data transfer sequence.

Current Address Read (Figure 8)

S
T
O
P

DATA

A
C
K

NO

A
C
K

S
T
A
R
T

SLAVE

ADDRESS

Bus Activity:
Master

SDA Line

Bus Activity:
NM24C04U/05U

DS800008-17

Random Read (Figure 9)

Sequential Read (Figure 10)

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NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

8-Pin Molded Small Outline Package (M8)

Package Number M08A

Physical Dimensions inches (millimeters) unless otherwise noted

8-Pin Molded Thin Shrink Small Outline Package

Package Number MTC08

1234

8765

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

Seating

Plane

0.004 - 0.010

(0.102 - 0.254)

0.014 - 0.020

(0.356 - 0.508)

0.014

(0.356)

Typ.

0.053 - 0.069

(1.346 - 1.753)

0.050

(1.270)

Typ

0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads

8° Max, Typ.

All leads

0.150 - 0.157

(3.810 - 3.988)

0.0075 - 0.0098
(0.190 - 0.249)

Typ. All Leads

0.04

(0.102)

All lead tips

0.010 - 0.020

(0.254 - 0.508)

x 45°

0.114 - 0.122
(2.90 - 3.10)

0.123 - 0.128
(3.13 - 3.30)

0.246 - 0.256
(6.25 - 6.5)

14

85

0.169 - 0.177
(4.30 - 4.50)

(7.72) Typ

(4.16) Typ

(1.78) Typ

(0.42) Typ

(0.65) Typ

0.002 - 0.006
(0.05 - 0.15)

0.0256 (0.65)
Typ.

0.0433
(1.1)

Max

0.0075 - 0.0098
(0.19 - 0.30)

Pin #1 IDENT

0.0035 - 0.0079

0°-8°

0.020 - 0.028
(0.50 - 0.70)

0.0075 - 0.0098
(0.19 - 0.25)

Seating

plane

Gage
plane

See detail A

Notes: Unless otherwise specified

1. Reference JEDEC registration MO153. Variation AA. Dated 7/93

Land pattern recommendation

DETAIL A

Typ. Scale: 40X

13

www.fairchildsemi.com

NM24C04U/NM24C05U Rev. C.1

NM24C04U/NM24C05U – 4K-Bit Serial EEPROM 2-Wire Bus Interface

Physical Dimensions inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N)

Package Number N08E

0.373 - 0.400

(9.474 - 10.16)

0.092

(2.337)

DIA

+

1234

8765

0.250 - 0.005

(6.35 ± 0.127)

87

0.032 ± 0.005

(0.813 ± 0.127)

Pin #1

Option 2

RAD

1

0.145 - 0.200

(3.683 - 5.080)

0.130 ± 0.005

(3.302 ± 0.127)

0.125 - 0.140

(3.175 - 3.556)

0.020

(0.508)

Min

0.018 ± 0.003

(0.457 ± 0.076)

90° ± 4°

Typ

0.100 ± 0.010

(2.540 ± 0.254)

0.040

(1.016)

0.039

(0.991)

Typ.

20° ± 1°

0.065

(1.651)

0.050

(1.270)

0.060

(1.524)

Pin #1 IDENT

Option 1

0.280

MIN

0.300 - 0.320
(7.62 - 8.128)

0.030

(0.762)

MAX

0.125

(3.175)

DIA

NOM

0.009 - 0.015

(0.229 - 0.381)

0.045 ± 0.015

(1.143 ± 0.381)

0.325

+0.040

-0.015

8.255

+1.016

-0.381

95° ± 5°

0.090

(2.286)

(7.112)

IDENT

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex­pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.

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