Page 1
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
Page 2
ADVANCE INFORMATION
NJ88C28
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
WITH NON-RESETTABLE COUNTERS
(Supersedes version in May 1992 Personal Communications IC Handbook)
T
he NJ88C28 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviated to 17 bits, when only the ‘A’ and ‘M’ counters require
changing.
The NJ88C28 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8715 series to produce
a universal binary coded synthesiser for up to 1100MHz
operation.
FEATURES
■
Low Power Consumption
■
High Performance Sample and Hold Phase Detector
■
Serial Input with Fast Update Feature
■
5V Operation
■
Fast Lock Up Time
■
SSOP Package Option
1
PDA
PDB
NC
LD
F
V
SS
V
DD
NC
OSC IN
PDA
PDB
NC
LD
F
V
V
NC
OSC IN
OSC OUT
NJ88C28
IN
9
1
IN
NJ88C28
SS
DD
10
Fig.1 Pin connections - top view (not to scale)
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
Input voltage
Open drain output, pin 4
All other pins
Storage temperature
DD−VSS
ORDERING INFORMATION
NJ88C28 IG MPES Miniature Plastic DIL Package
NJ88C28 IG NPAS Shrunk Miniature Plastic DIL Package
18
10
20
11
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
NC
OSC OUT
CH
RB
NC
MC
CAP
ENABLE
CLOCK
DATA
NC
NC
V
− 0·3V to V
SS
−55°C to +125°C
−0·75V to 7V
3119-4.2
MP18
NP20
7V
+ 0·3V
DD
OSC IN
OSC OUT
DATA
ENABLE
CLOCK
F
IN
V
DD
V
SS
9 (9)
10 (10)
12 (13)
14 (15)
13 (14)
5 (5)
7 (7)
6 (6)
REFERENCE COUNTER
(11 BITS)
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
‘M’ REGISTER
LATCH 1 LATCH 2 LATCH 3
‘M’ COUNTER
(10 BITS)
÷
CONTROL LOGIC
f
r
2
f
V
‘A’ REGISTER
LATCH 4 LATCH 5
‘A’ COUNTER
(7 BITS)
Fig.2 Block diagram (NP pinout shown in brackets)
RB CAP CH
17 15 18
(19) (16) (20)
SAMPLE/HOLD
PHASE
DETECTOR
FREQUENCY/
PHASE
DETECTOR
1 (1)
PDA
2 (2)
PDB
4 (4)
LOCK DETECT (LD)
V
SS
MODULUS
16 (17)
CONTROL
OUTPUT (MC)
Page 3
NJ88C28
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions, unless otherwise stated:
V
DD−VSS
DC Characteristics
Characteristic Units Conditions
Supply current 5·3 7·0 mA f
Modulus Control Output (MC)
High level 4·6 V I
Low level 0·4 V I
Lock Detect Output (LD)
Low level 0·4 V I
Open drain pull-up voltage 7·0 V
PDB Output
High level 4·6 V I
Low level 0·4 V I
3-state leakage current ±100 nA
Characteristics
AC
= 5V ±0·5V. Temperature range = − 40°C to +85°C
Value
Min. Typ. Max.
0.9 1·4 mA f
, f
osc
, f
osc
SOURCE
= 1mA
SINK
= 4mA
SINK
SOURCE
= 5mA
SINK
= 10MHz
FIN
= 4·096MHz
FIN
= 1mA
= 5mA
0 to 5V
square
wave
Characteristic
FIN and OSC IN input level
Max. operating frequency, F
and OSCIN inputs
IN
Propagation delay, clock to modulus control MC
Programming Inputs
Clock high time, t
Clock low time, t
Enable set-up time, t
Enable hold time, t
Data set-up time, t
Data hold time, t
CH
CL
ES
EH
DS
DH
Clock rise and fall times
High level threshold
Low level threshold
Hysteresis
Phase Detector
Positive going threshold, V
Negative going threshold, V
+
T
−
T
Digital phase detector propagation delay
RB current, I
RB
CAP/RB current gain, α
Programming capacitor, CAP
Output resistance, PDA, PDB
Value
Min. Typ. Max.
200
20
30
50
0·5
0·5
0·2
t
CH
0·2
0·2
0·2
0·2
V
−0·8
DD
0·8
1·0
2·0
V
−1·25
DD
V
+1·05
SS
500
1
6·9
7·8
600
9·0
53
80
Units Conditions
mV RMS
MHz
10MHz AC-coupled sinewave
Input squarewave V
25°C. See note 5.
ns
µs
µs
µs
µs
µs
µs
See note 2
All timing periods
are referenced to
the negative
transition of the
clock waveform
µs
V
V
V
See note 1
See note 1
See note 1
See note 3
V
V
ns
µA
Set by external conditions.
Over RB current range.
pF
C
plus packaging strays.
int
Ω
to VSS,
DD
NOTES
1. Data, Clock and Enable inputs are high impedance Schmitt buffers with typical thresholds of V
pull-up resistors and are therefore not TTL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically; 1µs for the sample and hold amplifier.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc.
frequency inputs.
5. The CAP reset device limits the minimum fin period due to its time constant formed by the CAP pin’s capacitance value. A typical R
1kΩ. Refer to AN112 for further details.
+0·8V and VDD−0·8V. These inputs do not have
SS
is about
DS(ON)
2
Page 4
PIN DESCRIPTIONS
NJ88C28
Pin no.
NP MP
1
2
3
4
5
6
7
8
9,10
9,10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
11
–
12
13
14
15
16
–
Name
PDA
PDB
NC
LD
F
IN
V
SS
V
DD
NC
OSC IN/
OSC OUT
NC
NC
DATA
CLOCK
ENABLE
CAP
MC
NC
Description
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
increases as fv (the output from the ‘M’ counter) phase lead increases; voltage decreases as fr (the
output from the ‘R’ counter) phase lead increases. Output is linear over only a narrow phase window,
determined by gain (programmed by RB). This pin is at (V
external loop filter amplifier biased to (V
DD−VSS
)/2. Ideally, V
window is centred between the thresholds, typically at 0·55(V
)/2 when the system is in lock, for an
DD−VSS
should be chosen such that the PDA
BIAS
DD−VSS
)
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f
or fv leading: positive pulses with respect to the bias point V
v >fr
f
< f
or fr leading: negative pulses with respect to the bias point V
v
r
BIAS
BIAS
fv = fr and phase error within PDA window: high impedance.
(Minimum,
M
= 3 for correct function of PDB).
Not connected.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply.
Not connected.
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 2·2kΩ resistor between pin 10 and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the total division ratio being
twice the programmed value i.e., 6 to 4094 in steps of 2.
Not connected.
Not connected.
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are three data words which control the NJ88C28;
MSB is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ‘R’ (11 bits).
Data is clocked on the negative transition of the CLOCK waveform. If less than 28 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘M’ and ‘A’ will have been
clocked in), then the ‘R’ counter latch will remain unchanged and only ‘M’ and ‘A’ will be transferred from
the input shift register to the counter latches. If 28 negative transitions have been counted, then the ‘R’
counter will be loaded with the new data.
When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to V
SS
).
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the
beginning of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes
high and remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters
are reset. This gives a total division ratio of
MP+A
, where P and
P
+1 represent the dual-modulus
prescaler values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers
with a division ratio up to and including ÷128/129. The programming range of the ‘M’ counter is 3-1023
but M
≥8 for correct PDA operation and, for correct operation with a prescaler, M ≥
possible channel is required, the minimum total division ratio N should be:
N ≥P
2
−
P
, where N =
A
. Where every
MP+A
Not connected
Continued...
.
3
Page 5
NJ88C28
PIN DESCRIPTIONS (continued)
Pin no.
NP MP
19
20
Name Description
17
18
RB
CH
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
SS
. I
RB
<600µA at V
An external hold capacitor should be connected between this pin and VSS.
PROGRAMMING
Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of the ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
where
fosc
= oscillator frequency,
fcomp
= comparison frequency,
R
= ‘R’ counter ratio
f
R
osc
=
2×
fcomp
For example, where the crystal frequency = 10MHz and a
channel spacing comparison frequency of 12·5kHz is required,
7
R
= = 400
10
2×12·5×10
3
Thus, the ‘R’ register would be programmed to 400 expressed
in binary. The total division ratio would then be 2×400 = 800
since the total division ratio of the ‘R’ counter plus the ÷2 stage
is from 6 to 4094 in steps of 2.
VCO Divider Chain
The synthesised frequency of the voltage controlled oscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(
P/P+1
)and the comparison frequency.
The division ratio
where M is the ratio of the ‘M’ counter in the range 3 to 1023
and A is the ratio of the ‘A’ counter in the range 1 to 127.
N = MP+A
,
= 5V.
DD
Note that
M ≥A
and
N
=
f
VCO
fcomp
For example, if the desired VCO frequency = 275MHz, the
comparison frequency is 12·5kHz and a two-modulus prescaler
of ÷64/65 is being used, then
6
Now, N =
275×10
N
= = 22 ×10
12·5×10
MP+A
, which can be rearranged as
3
3
N/P
=
M +A/P.
In our example we have P = 64, therefore
3
A
=
M
+
64
such that
22×10
64
M
= 343 and A/64 = 0.75.
Now, M is programmed to the integer part = 343 and A is
programmed to the fractional part×64 i.e., A = 0·75×64 = 48.
NB The minimum ratio
N
that can be used is
2
P
−
P
(4032 in our
example) for all contiguous channels to be available.
To check:
division ratio and is greater than 4032 ( =
N
= 343×64+48 = 22000, which is the required
2
P
−
P
).
When re-programming, the counters are changed only at
the zero state. There is no reset to zero, which means that the
synthesiser loop lock up time will be variable with respect to the
programming sequence timing. When only small changes in
frequency are required, the NJ88C28 non-resettable
synthesiser should achieve the shortest loop lock up times.
CLOCK
ENABLE
DATA
t
CH
t
EH
t
ES
t
DS
t
EH
t
DH
t
CL
t
ES
Fig. 3 Timing diagram showing timing periods required for correct operation
CLOCK
ENABLE
DATA
12
A
6
A
5
345
A
A
4
A
3
2
(15)26 (16)27 (17)28
(M2)R2(M1)R1(M0)R
0
Fig. 4 Timing diagram showing programming details
4
Page 6
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain:
K
K
VCO
PD
where
K
is the phase detector constant (volts/rad),
PD
VCO constant (rad/sec-volt) and N is the overall loop division
ratio. When N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain. The
sample and hold phase comparator in the NJ88C28 has a high
gain and uses a double sampling technique to reduce spurious
outputs to a low level.
A standard digital phase/frequency detector driving a threestate output, PDB, provides a ‘coarse’ error signal to enable
fast switching between channels.
The PDB output is active until the phase error is within the
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a ‘fine’
error signal to give further phase adjustment and to hold the loop
in lock. An internally generated ramp, controlled by the digital
output from both the reference and main divider chains, is
sampled at the reference frequency to give the ‘fine’ error signal,
PDA. When in phase lock, this output would be typically at the
bias voltage set by the external loop filter amplifier; any offset
from this would be proportional to phase error.
The relationship between this offset and the phase error is the
phase comparator gain,
external resistor, RB, and a capacitor, CAP. An internal 50pF
capacitor is used in the sample and hold comparator. Typically,
the gain is given by:
K
=
PDA
where
C
= internal 50pF+
CAP
deals with this further.
A hold capacitor (CH) of non-critical value, which might be
typically 470pF, is connected from pin 18 to V
N
K
, which is programmable with an
PDA
α
I
RB
2π
C
f
comp
CAP
C
.
Application Note AN112
EXT
. A smaller value
SS
K
is the
VCO
NJ88C28
is sufficient if the required sideband performance is not high.The
output from the sample and hold phase detector should be
combined with that of the coarse phase/frequency detector and
filtered to generate a single control voltage to drive the VCO. The
PDB gain is:
V
K
The stated minimum of 3 for the ‘M’ counter is true for the PDB
output only. To avoid race conditions in the internal phase
comparator counter for controlling the PDA timing, the minimum
division ratio for the ‘M’ counter should be 8 or more. Fig. 6 shows
a typical NJ88C28 application.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between pin 10 (OSC OUT) and the other components, as
shown in Fig. 5. A value of between 220Ω and 2·2kΩ is advised,
depending on the crystal series resistance.
NJ88C28
100
Fig. 5 Suggested crystal oscillator circuit
DD
=
PDB
4π
910
SERIES
68p
2·2k
5 – 65p
OSC IN
R2
VCO
s
C2
R3
C3
÷
P/P+1
R1a
R1b
f
out
V
BIAS
−
+
K
K
PDA
9
÷
R
+
÷
2
+
K
PDB
÷
M
1
2
F
5
in
NJ88C28
16
÷
A
MC
Fig.6 NJ88C28 application circuit
5
Page 7
NJ88C28
PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of V
may occur. When programming the device, DATA, ENABLE
and CLOCK pins must not exceed VDD as lock up times may be
compromised. A suggested interface to prevent this situation
is shown in Fig. 7.
V
(>VDD)
CC
PROGRAMMING
DEVICE
1N5711
Fig. 7 Suggested programming circuit
, as otherwise latch-up
DD
V
2k
DD
NJ88C28
LOOP EQUATIONS
1
2
0
K
3
) /{ (
−1
PDA
3
NC3 R
0
N f
comp
2
w
) −1}] / 2R
3
0
K
VCO KPD
N R C2 C3 R
K
VCO KPD R2
= [wo (2ζ+R)]
3
N
w
(1+2ζR)
0
K
K
VCO KPD
VCO KPD
N R
( R +2 ζ)
(2ζ+R)
ω
where
ω
=
0
ζ = [(
C3R
R
=
2
C
=
2
ω
= loop natural frequency
0
ζ = damping factor
R = ratio of real pole to ω
N
=
MP+A
or
provided
PDA window =
KPD = K
KPD = K
R
>> R
1a
V
−[(V
DD
PDA
PDB
1b
/
/
R
1a
R
1b
+) + (VT−)]
T
2π
Further details are to be found in Application Note AN112.
6
Page 8
NOTES
NJ88C28
7
Page 9
NJ88C28
PACKAGE DETAILS
Dimensions are shown thus: mm (in).
18
0-8°
CHAMFER
REF.
0·74 (0·029)
MAX.
(0·205/0·212)
5·20/5·38
SPOT REF.
1
(0·014/0·019)
18 LEADS AT
1·27 (0·050)
NOM. SPACING
11·35/11·79
(0·447/0·464)
7·07/7·33
(0·278/0·289)
20
PIN 1 IDENT
1
0·25/0·71
(0·010/0·028)
×45°
0·35/0·48
7·40/7·60
(0·291/0·299)
(0·093/0·104)
10·00/10·64
(0·394/0·419)
2·36/2·64
NOTES
0·10/0·30
(0·004/0·012)
1. Controlling dimensions are inches.
2. This package outline diagram is for guidance
only. Please contact your GPS Customer
Service Centre for further information.
18-LEAD MINIATURE PLASTIC DIL - MP18
11
7·65/7·90
(0·301/0·311)
10
(0·022/0·037)
0·23/0·33
(0·009/0·013)
0-8°
0·55/0·95
0·41/1·27
(0·016/0·050)
0·13/0·20
(0·005/0·008)
NOTES
1.Controlling dimensions are millimetres.
2. This package outline diagram is for guidance
only. Please contact your GPS Customer
Service Centre for further information.
1·68/1·78
(0·066/0·070)
(0·010/0·015)
20 LEADS AT
0·65 (0·0256)
NOM. SPACING
0·25/0·38
0·05/0·21
(0·002/0·008)
1·73/1·99
(0·065/0·078)
20-LEAD SHRUNK MINIATURE PLASTIC DIL (SSOP) - NP20
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (01793) 518000
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, CA95067-0017
United States of America.
Tel (408) 438 2900
Fax: (408) 438 5576
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
CUSTOMER SERVICE CENTRES
●
FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07
●
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●
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●
JAPAN Tokyo Tel: (3) 5276-5501 Fax: (3) 5276-5510
●
NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023.
●
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●
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●
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●
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Swindon Tel: 01793 518527/518566 Fax : 01793 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1994 Publication No. DS3119 Issue No. 4.2 April 1994
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
8
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