Datasheets NJ88C25 Datasheet

THIS DOCUMENT IS FOR MAINTENANCE

PURPOSES ONLY AND IS NOT

RECOMMENDED FOR NEW DESIGNS

NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS

NJ88C25

NJ88C25

FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)

T

he NJ88C25 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter, latched and buffered Band 0 and
Band 1 outputs and the necessary control and latch circuitry for
accepting and latching the input data.

Data is presented serially under external control from a suitable
microprocessor. Although 30 bits of data are initially required to
program all counters, subsequent updating can be abbreviated to
19 bits, when only the ‘A’, ‘M’ and ‘B’ counters require changing.

The NJ88C25 is intended to be used in conjunction with a two­modulus prescaler such as the SP8710 series to produce a
universal binary coded synthesiser.

FEATURES

■

Low Power Consumption

■

High Performance Sample and Hold Phase Detector

■

Serial Input with Fast Update Feature

ORDERING INFORMATION

NJ88C25 KA DG Ceramic DIL Package
NJ88C25 KA DP Plastic DIL Package
NJ88C25 KA MP Miniature Plastic DIL Package

1

PDA

2

PDB

3

F

V

4

LD

5

F

NJ88C25

IN

6

V

SS

7

V

DD

BAND 0

OSC IN

8
9

Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

Supply voltage, VDD2VSS:
Input voltage
Open drain output, pins 3 and 4:
All other pins:
Storage temperature:

18

CH

17

RB

16

MC

15

CAP

14

ENABLE

13

CLOCK

12

DATA

11

BAND 1

10

OSC OUT

DG18, DP18, MP18

20·5V to 7V

V

20·3V to VDD10·3V

265°C to 1150°C (DG package)

SS

255°C to 1125°C

(DP and MP packages)

DS3280-1.3

7V

OSC IN

OSC OUT

DATA

ENABLE

CLOCK

BAND 0
BAND 1

FIN

V

DD

V

SS

9

10

12
14

13

8
11

5

7
6

‘B’ REGISTER

LATCH 6

REFERENCE COUNTER

(11BITS)

LATCH 6 LATCH 7 LATCH 8

‘R’ REGISTER

‘M’ REGISTER

LATCH 1 LATCH 2 LATCH 3

‘M’ COUNTER

(10 BITS)

Fig.2 Block diagram

42

CONTROL LOGIC

f

r

f

V

‘A’ REGISTER

LATCH 4 LATCH 5

‘A’ COUNTER

(7 BITS)

RB CAP CH

17 15 18

SAMPLE/HOLD

PHASE

DETECTOR

FREQUENCY/

PHASE

DETECTOR

1

PDA

2

PDB

4

LOCK DETECT (LD)

V

SS

3

F

V

V

SS

MODULUS

16

CONTROL
OUTPUT (MC)

NJ88C25

ELECTRICAL CHARACTERISTICS AT VDD = 5V

Test conditions unless otherwise stated:

V

DC Characteristics

Characteristic Units Conditions

=2·7V to 5·5V. Temperature range = –30°C to +70°C

DD–VSS

Value

Min. Typ. Max.

Supply current 5·5 mA f

0·7 mA f
3·7 mA f

osc
osc
osc

, f

FIN

, f

FIN

, f

FIN

= 20MHz
= 1MHz
= 10MHz



0 to 5V



square



wave

OUTPUTS

Modulus Control (

High level V

Low level 0·4 V I

Lock Detect (

Low level 0·4 V I

MC), BAND 1 and BAND 2

LD) and F

V

20·4 V I

DD

SOURCE

= 1mA

SINK

= 4mA

SINK

= 1mA

Open drain pull-up voltage 7·0 V

PDB

High level 4·6 V I

Low level 0·4 V I

SOURCE

= 4mA

SINK

= 4mA

3-state leakage current ±0·1 µA

AC Characteristics

Value

Characteristic Units Conditions

Min. Typ. Max.

FIN and OSC IN input level 200 mV RMS 10MHz AC-coupled sinewave
Max. operating frequency, f
Propagation delay, clock to modulus control

FIN

and f

osc

20 MHz Input squarewave VDD to VSS,

MC 30 50 ns See note 2

Programming Inputs

Clock high time, t

Clock low time, t

CH

CL

Enable set-up time, t

Enable hold time, t

Data set-up time, t

Data hold time, t

EH

DS

DH

(see note 5) 0·2 t

ES

0·5 µs
0·5 µs

µs

CH

0·2 µs
0·2 µs
0·2 µs

Clock rise and fall times 0·2 µs

Positive threshold 3 V

Negative threshold 2 V





All timing periods



are referenced to



the negative




transition of the



clock waveform.



See note 5




TTL compatible, see note 1



Phase Detector

Digital phase detector propagation delay 500 ns

Gain programming resistor, RB 5 kΩ

Hold capacitor, CH 1 nF See note 3

Programming capacitor, CAP 1 nF

Output resistance, PDA 5 kΩ

NOTES

1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.

2. All counters have outputs directly synchronous with their respective clock rising edges.

3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant

to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.

4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and
FINinputs.

5. Clock to enable set-up time (tES) is variable, dependent on f
(tCL) and must meet the following conditions: 431/f

OSC<tES

. It needs to be specified in terms of f

OSC

,(tCH1tCL).

, clock high time (tCH) and clock low time

OSC

2

PIN DESCRIPTIONS

NJ88C25

Pin no. Name

1

2

3

4

5

6

7

9,10

PDA

PDB

F

V

LD

F

IN

V

SS

V

DD

OSC IN/

OSC OUT

8, 11

12

13

14

15

16

17

18

BAND 0/1

DATA

CLOCK

ENABLE

CAP

MC

RB

CH

Description

Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
increases as f

(the output from the ‘M’ counter) phase lead increases; voltage decreases as fr (the

v

output from the reference counter) phase lead increases. Output is linear over only a narrow phase
window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (V

DD2VSS

)/2 when the

system is in lock.

Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.

f

. fr or fv leading: positive pulses with respect to the bias point V

v

fv , fr or fr leading: negative pulses with respect to the bias point V
fv = fr and phase error within PDA window: high impedance.

BIAS

BIAS

This pin is an open drain output from the ‘M’ counter.

An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.

The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.

Negative supply (ground).

Positive supply (normally 5V)

These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground

to provide the necessary additional phase shift. The addition of a 220Ω resistor between OSC OUT and

the crystal will improve stability. An external reference signal may, alternatively, be applied to

OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the
programmed number.

Two latch outputs, providing an output of the data from the ‘B’ register.

Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are four data words which control the NJ88C25; MSB
is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ]B’ (2 bits) and ‘R’ (11 bits).

Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘B’,‘M’ and ‘A’ will have been
clocked in), then the ‘R’ counter latch will remain unchanged and only ‘M’ and ‘A’ will be transferred from
the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by
any glitches on the clock line after only ‘B’, ‘M’ and ‘A’ have been loaded. If 30 negative transitions have
been counted, then the ‘R’ counter will be loaded with the new data.

When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.

This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to V

Modulus control output for controlling an external dual-modulus prescaler.

MC will be low at the beginning

SS

).

of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of

MP1A

, where P and P11 represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation,
ratio N should be: N>

M>A

. Where every possible channel is required, the minimum total division

2

P

2P.

An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V

An external hold capacitor should be connected between this pin and V

SS

.

.

SS

3

NJ88C25

2·0

VDD = 5V
OSC IN, F

1·5

1·0

SUPPLY CURRENT (mA)

0·5

= 0V TO 5V SQUARE WAVE

IN

1 2 3 4 5 6 7 8 9 10

OSC IN

TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO
AND OSC IN

INPUT FREQUENCY (MHz)

FIN

FIN

8

7

6

5

4

3

SUPPLY CURRENT (mA)

2

1

0·2 0·4 0·6 0·8 1·0 1·2 1·4 1·6

VDD = 5V

= LOW FREQUENCY

F

IN

0V TO 5V SQUARE WAVE

10MHz

1MHz

INPUT LEVEL (V RMS)

Fig. 3 Typical supply current v. input frequency Fig. 4 Typical supply current v. input level, OSC IN

PROGRAMMING
Reference Divider Chain

The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.

where

fosc

= oscillator frequency,

fcomp

= comparison frequency,

R

= ‘R’ counter ratio

f

R

osc

=

23

fcomp

For example, where the crystal frequency = 10MHz and a
channel spacing comparison frequency of 12·5kHz is required,

7

R

= = 400

10

2312·5310

3

Thus, the ‘R’ register would be programmed to 400 expressed
in binary. The total division ratio would then be 23400 = 800
since the total division ratio of the ‘R’ counter plus the 42 stage
is from 6 to 4094 in steps of 2.

VCO Divider Chain

The synthesised frequency of the voltage controlled oscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(

P/P11

)and the comparison frequency .

The division ratio

where

M

is the ratio of the ‘M’ counter in the range 8 to 1023

N = MP1A

,

and A is the ratio of the ‘A’ counter in the range 0 to 127.
Note that M>A and

f

VCO

N

=

fcomp

For example, if the desired VCO frequency = 275MHz, the
comparison frequency is 12·5kHz and a two-modulus prescaler
of 464/65 is being used, then

275310

N

= = 22310

12·5310

6

3

Now, N = MP1A, which can be rearranged as
In our example we have P = 64, therefore

such that

3

22310

64

M

= 343 and A/64 = 0·75.

= M1

A

64

Now, M is programmed to the integer part = 343 and A is
programmed to the fractional part364 i.e., A = 0·75364 = 48.
NB The minimum ratio

N

that can be used is

our example) for all contiguous channels to be available.

To check: N = 343364148 = 22000, which is the required
division ratio and is greater than 4032 ( =

3

N/P

2

P

2P (=4032 in

2

P

2P).

= M1

A/P.

CLOCK

ENABLE

DATA

t

CH

t

EH

t

ES

t

DS

t

EH

t

DH

t

CL

t

ES

Fig. 5 Timing diagram showing timing periods required for correct operation

4

NJ88C25

CLOCK

ENABLE

DATA

12

A

6

A

5

345

A

A

4

3

Fig.6 Timing diagram showing programming details

PHASE COMPARATORS

Noise output from a synthesiser loop is related to loop gain:

K

K

VCO

PD

where

K

is the phase detector constant (volts/rad),

PD

the VCO constant (rad/sec/volt) and N is the overall loop division
ratio. When N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain.
The sample and hold phase comparator in the NJ88C25 has
a high gain and uses a double sampling technique to reduce
spurious outputs to a low level.

A standard digital phase/frequency detector driving a three­state output,PDB, provides a ‘coarse’ error signal to enable
fast switching between channels.

The PDB output is active until the phase error is within the

N

K

is

VCO

(17)28 (18)29 (19)30

A

2

(M2)R2(B1)R1(B0)R

0

sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on

LD. The sample and hold phase detector provides a
‘fine’ error signal to give further phase adjustment and to hold
the loop in lock. An internally generated ramp, controlled by the
digital output from both the reference and main divider chains,
is sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (V

DD2VSS

)/2 and any offset from this would be proportional

to phase error.

The relationship between this offset and the phase error is

the phase comparator gain,

K

, which is programmable with

PDA

an external resistor, RB, and a capacitor, CAP. An internal
50pF capacitor is used in the sample and hold comparator.

5

NJ88C25

HEADQUARTERS OPERATIONS

GEC PLESSEY SEMICONDUCTORS

Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: [phone]
Fax: [phone]

GEC PLESSEY SEMICONDUCTORS

P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: [phone]
Fax: [phone]

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Tel [phone] Fax: [phone].
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 GEC Plessey Semiconductors 1992 Publication No. DS3280 Issue No. 1.3 May 1992

This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury

or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.

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