Datasheets NJ8820 Datasheet

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NJ8820

FREQUENCY SYNTHESISER (PROM INTERFACE)

T

he NJ8820 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.

Data is presented as eight 4-bit words read from an external

memory, with the necessary timing signals generated internally.

It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.

The NJ8820 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of 230
Ceramic DIL package with operating temperature range of
240

°

C to 185°C.

FEATURES

■

Low Power Consumption

■ Direct Interface to ROM or PROM

■

High Performance Sample and Hold Phase Detector

■

>10MHz Input Frequency

ORDERING INFORMATION

NJ8820 BA DP Plastic DIL Package
NJ8820 BA MP Miniature Plastic DIL Package
NJ8820 MA DG Ceramic DIL Package

°

C to 170°C. The NJ8820MA is available only in

PDA

PDB

LD

F

IN

V

SS

V

DD

OSC IN

OSC OUT

D0

D1

1
2
3
4
5
6
7
8
9
10

NJ8820

20
19
18
17
16
15
14
13
12
11

Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

Supply voltage, VDD2V
Input voltage
Open drain outputs, pins 3 and 13
All other pins
Storage temperature

Storage temperature

SS

V

(DG package, NJ8820MA)

(DP and MP packages, NJ8820)

NJ8820

DS3277-1.2

CH

RB

MC

DS2

DS1

DS0

PE

ME

D3

D2

SS

DP20, MP20,

DG20

20·5V to 7V

20·3V to VDD10·3V

265°C to 1150°C
255°C to 1125°C

7V

PROGRAM

ENABLE (PE)

OSC IN

OSC OUT

D0



DATA

D1



INPUTS

D2



D3

F

V

DD

V

SS

MEMORY ENABLE

(ME)

14

PULSE

DETECT

7

8

9
10
11
12

4

IN

6

5

SEQUENCE

COUNTER

REFERENCE COUNTER

(11BITS)

LATCH 6 LATCH 7 LATCH 8

LATCH 4 LATCH 5

‘A’ COUNTER

(7 BITS)

CONTROL LOGIC

DATA SELECT

OUTPUTS

DS0 DS1 DS2

15 16 17

INTERNAL

LATCHES

42

LATCH 1 LATCH 2 LATCH 3

‘M’ COUNTER

(10 BITS)

TO

RB CH

19 2013

f

r

f

v

SAMPLE/HOLD

PHASE

DETECTOR

FREQUENCY/

PHASE

DETECTOR

1

PDA

2

PDB

3

LOCK DETECT (LD)

V

SS

MODULUS

18

CONTROL
OUTPUT (MC)

Fig.2 Block diagram

NJ8820

ELECTRICAL CHARACTERISTICS AT VDD = 5V

Test conditions unless otherwise stated:

V

DC Characteristics

=5V ±0·5V. Temperature range NJ8820 BA: –30°C to +70°C; NJ8820 MA: –40°C to +85°C

DD–VSS

Characteristic

Supply current

OUTPUT LEVELS
Memory Enable Output (

ME)

Low level

Open drain pull-up voltage

Data Select Outputs (DS0-DS2)

High level

Low level

Modulus Control Output (

MC)

High level

Low level

Lock Detect Output (

LD)

Low level

Open drain pull-up voltage

PDB Output

High level

Low level

3-state leakage current

INPUT LEVELS
Data Inputs (D0-D3)

High level

Low level

Program Enable Input (PE)

Trigger level

Min.

4·6

4·6

4·6

4·25

V

BIAS

6100mV

Value

Typ. Max.

3·5
0·7

5·5
1·5

0·4

0·4

0·4

0·4

0·4

60·1

0·75

Units

mA

f

, f

osc

mA

V

7

V

V
V

V
V

V

7

V

V
V

, f

f

osc

I

SINK

I

SOURCE

I

SINK

I

SOURCE

I

SINK

I

SINK

I

SOURCE

I

SINK

= 4mA

= 2mA

= 1mA

= 4mA

= 5mA

= 10MHz

FIN

= 1·0MHz

FIN

= 1mA

= 1mA

= 5mA

Conditions



0 to 5V




square
wave

µA

TTL compatible

V

See note 1

V

= self-bias point of PE

V

V

BIAS

(nominally V

DD

/2)

AC Characteristics

200

Value

Typ. Max.

Units

mVRMS

MHz

Conditions

10MHz AC-coupled sinewave
Input squarewave V

to VSS,

DD

Characteristic

and OSC IN input level

F

IN

Max. operating frequency, f

FIN

and f

osc

Min.

10·6

See note 5.
Propagation delay, clock to MC
PE pulse length, t
Data set-up time, t
Data hold time, t

DH

W

DS

5
1

10
Digital phase detector propagation delay
Gain programming resistor, RB

5
Hold capacitor, CH
Output resistance, PDA
Digital phase detector gain
Power supply rise time

NOTES

1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.

2. All counters have outputs directly synchronous with their respective clock rising edges.

3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant

to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically.

4. To ensure correct operation of power-on programming.

5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.

100

30

500

0·4

50

1
5

ns

µs
µs

ns
ns

kΩ

nF

kΩ

V/Rad

µs

See note 2.
Pulse to V

or VDD.

SS

See note 3.

10% to 90%, see note 4.

2

PIN DESCRIPTIONS

NJ8820

Pin no.

1

2

3

4

5

6

7, 8

9,10, 11, 12

13

14

15, 16, 17

18

19

20

2·0

VDD = 5V
OSC IN, F

1·5

Name

PDA

Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at
(VDD2VSS)/2 when the system is in lock. Voltage increases as fv phase lead increases; voltage
decreases as fr phase lead increases. Output is linear over only a narrow phase window, determined
by gain (programmed by RB).

PDB

LD

Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.

An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.

F

The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when

IN

a full logic swing is available, may be DC-coupled.

V

SS

V

DD

OSC IN/

OSC OUT

Negative supply (ground).

Positive supply.

These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.

D0-D3

Information on these inputs is transferred to the internal data latches during the appropriate data read
time slot. D3 is MSB, D0 is LSB.

ME

An open drain output for use in controlling the power supply to an external ROM or PROM.
during the data read period and high impedance at other times.

PE

A positive or negative pulse or edge AC-coupled into this pin initiates the single-shot data read
procedure. Grounding this pin repeats the data read procedure in a cyclic manner.

DS0-DS2

MC

Internally generated three-state data select outputs, which may be used to address external memory.

Modulus control output for controlling an external dual-modulus prescaler.
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation,
ratio should be

RB

An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V

CH

= 0V TO 5V SQUARE WAVE

IN

An external hold capacitor should be connected between this pin and VSS.

Description

f

. fr or fv leading: positive pulses with respect to the bias point V

v

fv , fr or fr leading: negative pulses with respect to the bias point V

BIAS

BIAS

fv = fr and phase error within PDA window: high impedance.

OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may

ME is low

MC will be low at the beginning

MP1A

, where P and P11 represent the dual-modulus prescaler

M>A

2

P

2P.

SS

. Where every possible channel is required, the minimum total division

.

8

7

6

VDD = 5V

= LOW FREQUENCY

F

IN

0V TO 5V SQUARE WAVE

5

4

3

SUPPLY CURRENT (mA)

2

1

0·2 0·4 0·6 0·8 1·0 1·2 1·4 1·6

1MHz

INPUT LEVEL (V RMS)

10MHz

1·0

SUPPLY CURRENT (mA)

0·5

1 2 3 4 5 6 7 8 9 10

OSC IN

F

IN

TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO
AND OSC IN

INPUT FREQUENCY (MHz)

FIN

Fig. 3 Typical supply current v. input frequency Fig. 4 Typical supply current v. input level, OSC IN

3

NJ8820

PROGRAMMING

Program information can be obtained from an external
ROM or PROM under the control of the NJ8820. Twenty-eight
data bits are required per channel arranged as eight 4-bit
words leaving four redundant bits, two of which are available
on the data bus driving the data transfer time slot and may be
used for external control purposes. A suitable PROM would be
the 74S287, giving up to 32 channel capability as shown in Fig.

5. Note that the choice of PNP transistor and supply bypass
capacitor on the ROM should be such that the ROM will power
up in time: for example, at 10MHz oscillator frequency, the

ROM must be powered up in less than 25µs.

Reading this data is normally done in single shot mode, with
the data read cycle started by either a positive or negative
pulse on the program enable (PE) pin. The data read cycle is
generated from a program clock at 1/64 of the reference
oscillator frequency. A memory enable signal (
to allow power-down of the ROM when it is not in use. Data
select outputs (DS0-DS2) remain in a high impedance state
when the program cycle is completed to allow the address bus
to be used for other functions if desired. The data map, data
read cycle and timing diagram are shown in Figs. 6 to 8. Data
is latched internally during the portions of the program cycle
shown shaded in Fig. 7 and all data is transferred to the

ME) is supplied

counters and latched during the data transfer time slot.

Alternatively, the PE pin may be grounded, causing the data
read cycle to repeat cyclically to allow continuous up-dating of
the program information. In this mode, external memory will be
enabled continuously (

ME low) and the data read cycle will
repeat every sixteen cycles of the internal program clock, i.e.
every 1024/f

seconds. This programming method is not

osc

recommended because the higher power consumption and
the possibilities of noise into the loop from the digital data lines.

Power-on Programming

On power-up, the data read cycle is automatically initiated,
making it unnecessary to provide a PE pulse. The circuit
detects the power supply rising above a threshold point
(nominally 1·5V) and, after an internally generated delay to
allow the supply to rise fully, the circuit is programmed in the
normal way. This delay is generated by counting reference
oscillator pulses and is therefore dependent on the crystal
used. The delay consists of 53248 reference oscillator cycles,
giving a delay of about 5ms at 10MHz.

To ensure correct operation of this function, the power
supply rise time should be less than 5ms (at 10MHz), rising
smoothly through the threshold point.

A4-A7

(CHANNEL SWITCH)

1
2
3
4
5
6
7
8

74S287

15V

100k

1·5k

16
15
14
13
12
11
10

9

0·1µ

10µ

D0

D1

1
2
3
4
5
6
7
8
9
10

NJ8820

20
19
18

DS2

17

DS1

16

DS0

15

PE

14

ME

13

D3

12

D2

11

C2B

22p

C2A

22p

C1

47p

C1 > C2A 1 C2B 1...

Fig. 5 Programming via PROM

WORD

DS2

1
2
3
4
5
6
7
8

DS1

0
0
0
0
1
1
1
1

DS0

0
0
1
1
0
0
1
1

D3

M1

0

M5

1

M9

0

A3

1
0

R3

1

R7

0
1

D2

M0
M4
M8

A2
A6

­R2
R6

R10

-

D1

M3
M7
A1
A5
R1
R5
R9

D0

-

­M2
M6
A0
A4
R0
R4
R8

Fig. 6 Data map

4

PROGRAM

CLOCK

PE

NJ8820

ME

DS0

DS1

DS2

4 PROGRAM CLOCK

CYCLES FROM SETTLING

PE

DS0

D0 - D3

t

W

(PE INTERNAL)

WORD1WORD2WORD3WORD4WORD5WORD6WORD7WORD

8

Fig.7 Data selection

DATA

TRANSFER

ON 2VE
CYCLE OF
PROGRAM

CLOCK

DATA

TRANSFER

Fig.8 Timing diagram

PHASE COMPARATORS

The digital phase/frequency detector drives a three-state
output, PDB, which provides a ‘coarse’ error signal to enable
fast switching between channels. The PDB output is active
until the phase error is within the sample and hold phase
detector, PDA, window, when PDB becomes high impedance.
Phase-lock is indicated at this point by a low level on
sample and hold phase detector provides a ‘fine’ error signal
to give further phase adjustment and to hold the loop in lock.

An internally generated ramp, controlled by the digital
output from both the reference and main divider chains, is
sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (V

DD2VSS

)/2 and any offset from this would be proportional

to phase error. The relationship between this offset and the

LD. The

t

t

DS

DH

(DATA - INTERNAL

MODE)

phase error is the phase comparator gain, which is
programmable with an external resistor, RB. An internal 50pF
capacitor is used in the sample and hold comparator.

CRYSTAL OSCILLATOR

When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between pin 8 (OSC OUT) and the other components. A value

of 2·2kΩ is advised.

PROGRAMMING/POWER UP

Data and signal input pins should not have input applied to
them prior to the application of V
occur.

, as otherwise latch-up may

DD

5

NJ8820

HEADQUARTERS OPERATIONS

GEC PLESSEY SEMICONDUCTORS

Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: [phone]
Fax: [phone]

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• SOUTH EAST ASIA Singapore Tel: [phone] Fax: [phone]

GEC PLESSEY SEMICONDUCTORS

P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.

• SWEDEN Stockholm, Tel: [phone] Fax: [phone]

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These are supported by Agents and Distributors in major countries world-wide.
Tel: [phone]
Fax: [phone]

This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury

or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.

 GEC Plessey Semiconductors 1992

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of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee ex press or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

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