Datasheet NG80960KA-16, NG80960KA-25 Datasheet (Intel Corporation)

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. May 1993
© INTEL CORPORATION, 1993 Order Number: 270775-005

80960KA

EMBEDDED 32-BIT MICROPROCESSOR

The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large
register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,
this high performance processor is capable of execution rates in excess of 9.4 million instructions per second

*

.
The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and
specialty instrumentation.

Figure 1. The 80960KA Processor’s Highly Parallel Architecture

* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Corporation)

■ High-Performance Embedded Architecture

— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz

■ 512-Byte On-Chip Instruction Cache

— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-

tions

■ Multiple Register Sets

— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding

■ 4 Gigabyte, Linear Address Space

■ Pin Compatible with 80960KB

■ Built-in Interrupt Controller

— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz

■ Easy to Use, High Bandwidth 32-Bit Bus

— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst

■ 132-Lead Packages:

— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)

SIXTEEN

32-BIT GLOBAL

REGISTERS

64- BY 32-BIT

LOCAL

REGISTER

CACHE

32-BIT

INSTRUCTION

EXECUTION

UNIT

INSTRUCTION

FETCH UNIT

512-BYTE

INSTRUCTION

CACHE

INSTRUCTION

DECODER

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

BUS

CONTROL

LOGIC

32-BIT

BURST

BUS

ii

1.0 THE i960® PROCESSOR ................................ 1

1.1. Key Performance Features .......................... 2

1.1.1. Memory Space And Addressing Modes . 4

1.1.2. Data Types ............................................. 4

1.1.3. Large Register Set ................................. 4

1.1.4. Multiple Register Sets ............................ 5

1.1.5. Instruction Cache ................................... 5

1.1.6. Register Scoreboarding ......................... 5

1.1.7. High Bandwidth Local Bus ..................... 6

1.1.8. Interrupt Handling ................................... 6

1.1.9. Debug Features ..................................... 6

1.1.10. Fault Detection ..................................... 7

1.1.11. Built-in Testability ................................. 7

1.1.12. CHMOS ................................................ 7

2.0 ELECTRICAL SPECIFICATIONS .................. 10

2.1. Power and Grounding ................................ 10

2.2. Power Decoupling Recommendations ....... 10

2.3. Connection Recommendations .................. 11

2.4. Characteristic Curves ................................. 11

2.5. Test Load Circuit ........................................ 14

2.6. Absolute Maximum Ratings ....................... 15

2.7. DC Characteristics ..................................... 15

2.8. AC Specifications ....................................... 16

2.8.1. AC Specification Tables ....................... 17

3.0 MECHANICAL DATA ..................................... 21

3.1. Packaging .................................................. 21

3.1.1. Pin Assignment .................................... 21

3.2. Pinout ......................................................... 25

3.3. Package Thermal Specification ................. 29

4.0. WAVEFORMS ............................................... 33

5.0. REVISION HISTORY ..................................... 38

FIGURES

Figure 1. The 80960KA Processor’s Highly

Parallel Architecture ............................ i

Figure 2. 80960KA Programming

Environment ........................................ 1

Figure 3. Instruction Formats ............................. 4

Figure 4. Multiple Register Sets Are Stored

On-Chip ...............................................6

Figure 5. Connection Recommendations

for Low Current Drive Network ..........11

Figure 6. Connection Recommendations

for High Current Drive Network ......... 11

Figure 7. Typical Supply Current vs.

Case Temperature ............................12

Figure 8. Typical Current vs. Frequency

(Room Temp) .................................... 12

Figure 9. Typical Current vs. Frequency

(Hot Temp) ........................................ 13

Figure 10. Worst-Case Voltage vs. Output

Current on Open-Drain Pins .............. 13

Figure 11. Capacitive Derating Curve ................13

Figure 12. Test Load Circuit for Three-State

Output Pins ......................................14

Figure 13. Test Load Circuit for Open-Drain

Output Pins ......................................14

Figure 14. Drive Levels and Timing Relationships

for 80960KA Signals ......................... 16

Figure 15. Processor Clock Pulse (CLK2) .......... 20

Figure 16. RESET Signal Timing ....................... 20

Figure 17. 32-Lead Pin-Grid Array

(PGA) Package .................................21

Figure 18. 80960KA PGA Pinout—View from

Bottom (Pins Facing Up) ................... 22

Figure 19. 80960KA PGA Pinout—View from

Top (Pins Facing Down) ....................23

Figure 20. 80960KA 132-Lead Plastic Quad

Flat-Pack (PQFP) Package ...............23

Figure 21. PQFP Pinout - View From Top .......... 24

Figure 22. HOLD Timing .................................... 30

Figure 23. 16 MHz Maximum Allowable

Ambient Temperature ....................... 31

80960KA

EMBEDDED 32-BIT MICROPROCESSOR

CONTENTS

iii

Figure 24. 20 MHz Maximum Allowable

Ambient Temperature ....................... 31

Figure 25. 25 MHz Maximum Allowable

Ambient Temperature ....................... 32

Figure 26. Maximum Allowable Ambient

Temperature for the Extended
Temperature TA-80960KA at

20 MHz in PGA Package .................. 32

Figure 27. Non-Burst Read and Write

Transactions Without Wait States ..... 33

Figure 28. Burst Read and Write Transaction

Without Wait States ......................... 34

Figure 29. Burst Write Transaction with

2, 1, 1, 1 Wait States ........................ 35

Figure 30. Accesses Generated by Quad Word

Read Bus Request, Misaligned Two
Bytes from Quad Word Boundary

(1, 0, 0, 0 Wait States) ...................... 36

Figure 31. Interrupt Acknowledge Transaction .. 37

TABLES

Table 1. 80960KA Instruction Set .....................3

Table 2. Memory Addressing Modes ................ 4

Table 3. 80960KA Pin Description:

L-Bus Signals ...................................... 8

Table 4. 80960KA Pin Description:

Support Signals ...................................9

Table 5. DC Characteristics ............................15

Table 6. 80960KA AC Characteristics

(16 MHz) ........................................... 17

Table 7. 80960KA AC Characteristics

(20 MHz) ........................................... 18

Table 8. 80960KA AC Characteristics

(25 MHz) ........................................... 19

Table 9. 80960KA PGA Pinout —

In Pin Order .......................................25

Table 10. 80960KA PGA Pinout —

In Signal Order .................................. 26

Table 11. 80960KA PQFP Pinout —

In Pin Order .......................................27

Table 12. 80960KA PQFP Pinout —

In Signal Order .................................. 28

Table 13. 80960KA PGA Package

Thermal Characteristics ....................29

Table 14. 80960KA PQFP Package

Thermal Characteristics ....................30

80960KA

1

1.0 THE i960® PROCESSOR

The 80960KA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
were especially designed to serve the needs of
embedded applications. The embedded market
includes applications as diverse as industrial
automation, avionics, image processing, graphics and
networking. These types of applications require high
integration, low power consumption, quick interrupt
response times and high performance. Since time to
market is critical, embedded microprocessors need to
be easy to use in both hardware and software
designs.

All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.

Software written for the 80960KA will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KB
which includes an integrated floating-point unit and
the 80960MC which is a military-grade version that
supports multitasking, memory management, multi­processing and fault tolerance.

Figure 2. 80960KA Programming Environment

INSTRUCTION CACHE

INSTRUCTION

STREAM

FETCH LOAD STORE

SIXTEEN 32-BIT GLOBAL REGISTERS

g0

g15

SIXTEEN 32-BIT LOCAL REGISTERS

REGISTER CACHE

FOUR 80-BIT FLOATING POINT REGISTERS

r0

r15

CONTROL REGISTERS

INSTRUCTION

EXECUTION

INSTRUCTION

POINTER

ARITHMETIC

CONTROLS

PROCESS

CONTROLS

TRACE

CONTROLS

ARCHITECTURALLY

DEFINED

DATA STRUCTURES

FFFF FFFFH0000 0000H

ADDRESS SPACE

PROCESSOR STATE

REGISTERS

80960KA

2

1.1. Key Performance Features

The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KA’s exceptional
performance:

1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the
80960KA provides thirty-two 32-bit registers. (See
Figure 2.)

2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most programs so
that execution speed can be improved by ensuring
that these core instructions are executed as quickly
as possible. The most frequently executed instruc­tions such as register-register moves, add/subtract,
logical operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)

3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of times that
the processor must access memory to perform an
operation. As with other processors based on RISC
technology, the 80960KA has a Load/Store archi­tecture. As such, only the LOAD and STORE instruc­tions reference memory; all other instructions operate
on registers. This type of architecture simplifies
instruction decoding and is used in combination with
other techniques to increase parallelism.

4. Simple Instruction Formats. All instructions in
the 80960KA are 32 bits long and must be aligned on
word boundaries. This alignment makes it possible to
eliminate the instruction alignment stage in the
pipeline. To simplify the instruction decoder, there are
only five instruction formats; each instruction uses
only one format. (See Figure 3.)

5. Overlapped Instruction Execution. Load
operations allow execution of subsequent instructions
to continue before the data has been returned from
memory, so that these instructions can overlap the
load. The 80960KA manages this process transpar­ently to software through the use of a register score­board. Conditional instructions also make use of a
scoreboard so that subsequent unrelated instructions
may be executed while the conditional instruction is
pending.

6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value is sent
immediately to its destination register. Yet at the same
time, the value is put on a bypass path to the ALU,
thereby saving the time that otherwise would be
required to retrieve the value for the next operation.

7. Bandwidth Optimizations. The 80960KA gets
optimal use of its memory bus bandwidth because the
bus is tuned for use with the on-chip instruction
cache: instruction cache line size matches the
maximum burst size for instruction fetches. The
80960KB automatically fetches four words in a burst
and stores them directly in the cache. Due to the size
of the cache and the fact that it is continually filled in
anticipation of needed instructions in the program
flow, the 80960KA is relatively insensitive to memory
wait states. The benefit is that the 80960KA delivers
outstanding performance even with a low cost
memory system.

8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then sends
it on to the instruction decoder at the same time it
updates the cache. Thus, no extra time is spent to
load and read the cache.

80960KA

3

Table 1. 80960KA Instruction Set

Data Movement Arithmetic Logical Bit and Bit Field

Load
Store
Move
Load Address

Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift

And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Exclusive Nor
Not
Nand
Rotate

Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modify

Comparison Branch Call/Return Fault

Compare
Conditional Compare
Compare and Increment
Compare and Decre­ment

Unconditional Branch
Conditional Branch
Compare and Branch

Call
Call Extended
Call System
Return
Branch and Link

Conditional Fault
Synchronize Faults

Debug Miscellaneous Decimal

Modify Trace Controls
Mark
Force Mark

Atomic Add
Atomic Modify
Flush Local Registers
Modify Arithmetic Con­trols
Scan Byte for Equal
Test Condition Code
Modify Process Controls

Decimal Move
Decimal Add with Carry
Decimal Subtract with
Carry

Synchronous

Synchronous Load
Synchronous Move

80960KA

4

Figure 3. Instruction Formats

Opcode Displacement

Opcode Reg/Lit Reg M Displacement

Opcode Reg Reg/Lit Modes Ext’d Op Reg/Lit

Opcode Reg Base M X Offset

Opcode Reg Base Mode Scale xx Offset

Displacement

Control

Compare and

Branch

Register to

Register

Memory Access—

Short

Memory Access—

Long

1.1.1. Memory Space And Addressing Modes

The 80960KA offers a linear programming environ­ment so that all programs running on the processor
are contained in a single address space. Maximum
address space size is 4 Gigabytes (2

32

bytes).

For ease of use the 80960KA has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the modes.

Table 2. Memory Addressing Modes

• 12-Bit Offset

• 32-Bit Offset

• Register-Indirect

• Register + 12-Bit Offset

• Register + 32-Bit Offset

• Register + (Index-Register x Scale-Factor)

• Register x Scale Factor + 32-Bit Displacement

• Register + (Index-Register x Scale-Factor) +
32-Bit Displacement

• Scale-Factor is 1, 2, 4, 8 or 16

1.1.2. Data Types

The 80960KA recognizes the following data types:
Numeric:

• 8-, 16-, 32- and 64-bit ordinals

• 8-, 16-, 32- and 64-bit integers
Non-Numeric:

• Bit

• Bit Field

• Triple Word (96 bits)

• Quad-Word (128 bits)

1.1.3. Large Register Set

The 80960KA programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which leads
to greater instruction processing speed.

There are two types of general-purpose registers:
local and global. The global registers consist of
sixteen 32-bit registers (G0 though G15). These
registers perform the same function as the general-

80960KA

5

purpose registers provided in other popular micropro­cessors. The term global refers to the fact that these
registers retain their contents across procedure calls.

The local registers, on the other hand, are procedure
specific. For each procedure call, the 80960KA
allocates 16 local registers (R0 through R15). Each
local register is 32 bits wide.

1.1.4. Multiple Register Sets

To further increase the efficiency of the register set,
multiple sets of local registers are stored on-chip (See
Figure 4). This cache holds up to four local register
frames, which means that up to three procedure calls
can be made without having to access the procedure
stack resident in memory.

Although programs may have procedure calls nested
many calls deep, a program typically oscillates back
and forth between only two to three levels. As a
result, with four stack frames in the cache, the proba­bility of having a free frame available on the cache
when a call is made is very high. In fact, runs of repre­sentative C-language programs show that 80% of the
calls are handled without needing to access memory.

If four or more procedures are active and a new
procedure is called, the 80960KA moves the oldest
local register set in the stack-frame cache to a
procedure stack in memory to make room for a new
set of registers. Global register G15 is the frame
pointer (FP) to the procedure stack.

Global registers are not exchanged on a procedure
call, but retain their contents, making them available
to all procedures for fast parameter passing.

1.1.5. Instruction Cache

To further reduce memory accesses, the 80960KA
includes a 512-byte on-chip instruction cache. The
instruction cache is based on the concept of locality
of reference; most programs are not usually executed
in a steady stream but consist of many branches,
loops and procedure calls that lead to jumping back
and forth in the same small section of code. Thus, by
maintaining a block of instructions in cache, the
number of memory references required to read
instructions into the processor is greatly reduced.

To load the instruction cache, instructions are fetched
in 16-byte blocks; up to four instructions can be
fetched at one time. An efficient prefetch algorithm
increases the probability that an instruction will
already be in the cache when it is needed.

Code for small loops often fits entirely within the
cache, leading to a great increase in processing
speed since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
will be there on the procedure’s return.

1.1.6. Register Scoreboarding

The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by using register scoreboarding.

Register scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
contents is accompanied by a test of the scoreboard
bit to ensure that the load has completed before
processing continues. Since the processor does not
need to wait for the LOAD to complete, it can execute
additional instructions placed between the LOAD and
the instruction that uses the register contents, as
shown in the following example:

ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add R4, R5, R6

In essence, the two unrelated instructions between
LOAD and ADD are executed “for free” (i.e., take no
apparent time to execute) because they are executed
while the register is being loaded. Up to three load
instructions can be pending at one time with three
corresponding scoreboard bits set. By exploiting this
feature, system programmers and compiler writers
have a useful tool for optimizing execution speed.

80960KA

6

Figure 4. Multiple Register Sets Are Stored On-Chip

REGISTER

CACHE

ONE OF FOUR

LOCAL

REGISTER SETS

LOCAL REGISTER SET

R

15

R

0

31

0

1.1.7. High Bandwidth Local Bus

The 80960KA CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus). The
L-Bus provides a direct communication path between
the processor and the memory and I/O subsystem
interfaces. The processor uses the L-Bus to fetch
instructions, manipulate memory and respond to
interrupts. L-Bus features include:

• 32-bit multiplexed address/data path

• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time

• High bandwidth reads and writes with

66.7 MBytes/s burst (at 25 MHz)

Table 3 defines L-bus signal names and functions;
Table 4 defines other component-support signals
such as interrupt lines.

1.1.8. Interrupt Handling

The 80960KA can be interrupted in two ways: by the
activation of one of four interrupt pins or by sending a
message on the processor’s data bus.

The 80960KA is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip

interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.

1.1.9. Debug Features

The 80960KA has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers: the Process-Controls Word and the Trace­Controls Word. By setting bits in these control words,
a software debug monitor can closely control how the
processor responds during program execution.

The 80960KA provides two hardware breakpoint
registers on-chip which, by using a special command,
can be set to any value. When the instruction pointer
matches either breakpoint register value, the
breakpoint handling routine is automatically called.

The 80960KA also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution at
that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.

Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special

80960KA

7

debug instruction. In each case, the 80960KA
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until the
routine completes, at which time execution resumes
at the next instruction. The 80960KA’s tracing
mechanisms, implemented completely in hardware,
greatly simplify the task of software test and debug.

1.1.10. Fault Detection

The 80960KA has an automatic mechanism to handle
faults. Fault types include trace and arithmetic faults.
When the processor detects a fault, it automatically
calls the appropriate fault handling routine and saves
the current instruction pointer and necessary state
information to make efficient recovery possible. Like
interrupt handling routines, fault handling routines are
usually written to meet the needs of specific applica­tions and are often included as part of the operating
system or kernel.

For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. The fault handler can use this specific infor­mation to respond correctly to the fault.

1.1.11. Built-in Testability

Upon reset, the 80960KA automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960KA asserts its FAILURE
pin and will not begin program execution. Self test
takes approximately 47,000 cycles to complete.

System manufacturers can use the 80960KA’s self­test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field, the
self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.

1.1.12. CHMOS

The 80960KA is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semicon­ductor) process. The 80960KA is currently available
in 16, 20 and 25 MHz versions.

80960KA

8

Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)

NAME TYPE DESCRIPTION

CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is divided

by two inside the 80960KA to generate the internal processor clock.

LAD31:0 I/O

T.S.

LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
from memory. During an address (T

a

) cycle, bits 2-31 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (T

d

) cycle, bits 0-31

contain read or write data. These pins float to a high impedance state when not
active.

Bits 0-1 comprise SIZE during a T

a

cycle. SIZE specifies burst transfer size in words.

LAD1 LAD0

0 0 1 Word
0 1 2 Words
1 0 3 Words
1 1 4 Words

ALE

O

T.S.

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a T

a

cycle and deasserted before the beginning of the Td state. It is

active LOW and floats to a high impedance state during a hold cycle (T

h

).

ADS

O

O.D.

ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T

a

state and deasserted during the following Td state. For a burst transaction, ADS is
asserted again every T

d

state where READY was asserted in the previous cycle.

W/R

O

O.D.

WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It
is latched on-chip and remains valid during T

d

cycles.

DT/R

O

O.D.

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
L-Bus. It is low during T

a

and Td cycles for a read or interrupt acknowledgment; it is

high during T

a

and Td cycles for a write. DT/R never changes state when DEN is

asserted.

READY

I READY indicates that data on LAD lines can be sampled or removed. IfREADY is not

asserted during a T

d

cycle, the Td cycle is extended to the next cycle by inserting a

wait state (T

w

) and ADS is not asserted in the next cycle.

LOCK

I/O

O.D.

BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK

.

At the start of a RMW operation, the processor examines the LOCK

pin. If the pin is
already asserted, the processor waits until it is not asserted. If the pin is not asserted,
the processor asserts LOCK

during the Ta cycle of the read transaction. The

processor deasserts LOCK

in the Ta cycle of the write transaction. During the time

LOCK

is asserted, a bus agent can perform a normal read or write but not a RMW

operation.
The processor also asserts LOCK

during interrupt-acknowledge transactions.

Do not leave LOCK

unconnected. It must be pulled high for the processor to function

properly.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

80960KA

9

BE3:0 O

O.D.

BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used
in the current bus cycle. BE3

corresponds to LAD31:24; BE0 corresponds to LAD7:0.

The byte enables are provided in advance of data:

• Byte enables asserted during T

a

specify the bytes of the first data word.

• Byte enables asserted during T

d

specify the bytes of the next data word, if any (the

word to be transmitted following the next assertion of READY

).

Byte enables that occur during T

d

cycles that precede the last assertion of READY

are undefined. Byte enables are latched on-chip and remain constant from one T

d

cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor will actually use. L-Bus

agents are required to assert only adjacent byte enables (e.g., asserting just BE0

and

BE2

is not permitted) and are required to assert at least one byte enable. Address

bits A

0

and A1 can be decoded externally from the byte enables.

HOLD I HOLD: A request from an external bus master to acquire the bus. When the

processor receives HOLD and grants bus control to another master, it floats its three­state bus lines and open-drain control lines, asserts HLDA and enters the T

h

state.

When HOLD deasserts, the processor deasserts HLDA and enters the T

i

or Ta state.

HLDA O

T.S.

HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has
relinquished control of the bus.

CACHE O

T.S.

CACHE indicates when an access is cacheable during a T

a

cycle. It is not asserted

during any synchronous access, such as a synchronous load or move instruction
used for sending an IAC message. The CACHE signal floats to a high impedance
state when the processor is idle.

Table 4. 80960KA Pin Description: Support Signals (Sheet 1 of 2)

NAME TYPE DESCRIPTION

BADAC

I BAD ACCESS, if asserted in the cycle following the one in which the lastREADY of a

transaction is asserted, indicates an unrecoverable error occurred on the current bus
transaction or a synchronous load/store instruction has not been acknowledged.

During system reset the BADAC

signal is interpreted differently. If the signal is high, it
indicates that this processor will perform system initialization. If it is low, another
processor in the system will perform system initialization instead.

RESET I RESET clears the processor’s internal logic and causes it to reinitialize.

During RESET assertion, the input pins are ignored (except for BADAC

and

IAC

/INT0), the three-state output pins are placed in a high impedance state and other
output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The

HIGH to LOW transition of RESET should occur after the rising edge of both CLK2
and the external bus clock and before the next rising edge of CLK2.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 2 of 2)

NAME TYPE DESCRIPTION

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

80960KA

10

FAILURE O

O.D.

INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
After RESET deasserts and before the first bus transaction begins, FAILURE

asserts
while the processor performs a self-test. If the self-test completes successfully, then
FAILURE

deasserts. The processor then performs a zero checksum on the first eight

words of memory. If it fails, FAILURE

asserts for a second time and remains

asserted. If it passes, system initialization continues and FAILURE

remains

deasserted.

IAC

/INT

0

I INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC

message or an interrupt is pending. The bus interrupt control register determines how
the signal is interpreted. To signal an interrupt or IAC request in a synchronous
system, this pin — as well as the other interrupt pins — must be enabled by being
deasserted for at least one bus cycle and then asserted for at least one additional
bus cycle. In an asynchronous system the pin must remain deasserted for at least
two bus cycles and then asserted for at least two more bus cycles.

During system reset, this signal must be in the logic high condition to enable normal
processor operation. The logic low condition is reserved.

INT

1

I INTERRUPT 1, like INT0, provides direct interrupt signaling.

INT

2

/INTR I INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines

how this pin is interpreted. If INT

2

, it has the same interpretation as the INT0 and INT

1

pins. If INTR, it is used to receive an interrupt request from an external interrupt
controller.

INT

3

/INTA I/O

O.D.

INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. If INT

3

, it has the same interpretation as the

INT

0

, INT1 and INT2 pins. If INTA, it is used as an output to control interrupt-

acknowledge transactions. The INTA

output is latched on-chip and remains valid

during T

d

cycles; as an output, it is open-drain.

N.C. N/A NOT CONNECTED indicates pins should not be connected. Never connect any pin

marked N.C. as these pins may be reserved for factory use.

Table 4. 80960KA Pin Description: Support Signals (Sheet 2 of 2)

NAME TYPE DESCRIPTION

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

2.0 ELECTRICAL SPECIFICATIONS

2.1. Power and Grounding

The 80960KA is implemented in CHMOS IV
technology and therefore has modest power require­ments. Its high clock frequency and numerous output
buffers (address/data, control, error and arbitration
signals) can cause power surges as multiple output
buffers simultaneously drive new signal levels. For
clean on-chip power distribution, V

CC

and VSS pins
separately feed the device’s functional units. Power
and ground connections must be made to all
80960KA power and ground pins. On the circuit
board, all V

cc

pins must be strapped closely together,

preferably on a power plane; all V

ss

pins should be

strapped together, preferably on a ground plane.

2.2. Power Decoupling
Recommendations

Place a liberal amount of decoupling capacitance
near the 80960KA. When driving the L-bus the
processor can cause transient power surges, particu­larly when connected to a large capacitive load.

Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance is reduced by shortening
board traces between the processor and decoupling
capacitors as much as possible.

80960KA

11

2.3. Connection Recommendations

For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, if one or
more interrupt lines are not used, they should be
pulled up. No inputs should ever be left floating.

All open-drain outputs require a pullup device. While
in most cases a simple pullup resistor is adequate, a
network of pullup and pulldown resistors biased to a
valid V

IH

(>3.0 V) and terminated in the characteristic
impedance of the circuit board is recommended to
limit noise and AC power consumption. Figure 5 and
Figure 6 show recommended values for the resistor
network for low and high current drive, assuming a
characteristic impedance of 100

Ω. Terminating
output signals in this fashion limits signal swing and
reduces AC power consumption.

NOTE:
Do not connect external logic to pins marked N.C.

Figure 5. Connection Recommendations

for Low Current Drive Network

220 Ω

330 Ω

Low Drive Network:

V

OH

= 3.0 V

I

OL

= 20.7 mA

V

CC

OPEN-DRAIN OUTPUT

Figure 6. Connection Recommendations

for High Current Drive Network

2.4. Characteristic Curves

Figure 7 shows typical supply current requirements
over the operating temperature range of the
processor at supply voltage (V

CC

) of 5 V. Figure 8 and

Figure 9 show the typical power supply current (I

CC

)
that the 80960KA requires at various operating
frequencies when measured at three input voltage
(V

CC

) levels and two temperatures.

For a given output current (I

OL

) the curve in Figure 10

shows the worst case output low voltage (V

OL

). Figure
11 shows the typical capacitive derating curve for the
80960KA measured from 1.5V on the system clock
(CLK) to 1.5V on the falling edge and 1.5V on the
rising edge of the L-Bus address/data (LAD) signals.

OPEN-DRAIN OUTPUT

180

Ω

390 Ω

High Drive Network:

V

OH

= 3.4 V

I

OL

= 25.3 mA

V

CC

80960KA

12

Figure 7. Typical Supply Current vs. Case Temperature

Figure 8. Typical Current vs. Frequency (Room Temp)

-60 -40 -20 0 20 40 60 80 100 120 140

VCC = 5.0 V

POWER SUPPLY CURRENT (mA)

CASE TEMPERATURE (°C)

25 MHz
20 MHz
16 MHz

380
360
340
320
300
280
260

240
220
200

OPERATING FREQUENCY (MHz)

@4.5V

@5.0V

@5.5V

TYPICAL SUPPLY CURRENT (mA)

TEMP = +22°C

400

380

360

340

320

300

280

260

240

220

200
180

16 20 25

80960KA

13

Figure 9. Typical Current vs. Frequency (Hot Temp)

OPERATING FREQUENCY (MHz)

@4.5V

@5.0V

@5.5V

TYPICAL SUPPLY CURRENT (mA)

TEMP = +22°C

380

360

340

320

300

280

260

240

220

200
180

16 20 25

160

Figure 10. Worst-Case Voltage vs. Output Current

on Open-Drain Pins

0 10 20 30 40 50

0.8

0.6

0.4

0.2

0.0

OUTPUT LOW CURRENT(mA)

(TEMP = +85°C, V

CC

= 4.5V)

OUTPUT LOW VOLTAGE (V)

Figure 11. Capacitive Derating Curve

0 20 40 60 80 100

30
25
20
15
10

CAPACITIVE LOAD(pF)

(TEMP = +85°C, V

CC

= 4.5V)

5
0

RISING

FALLING

VALID DELAY(ns)

THREE-STATE OUTPUT

80960KA

14

2.5. Test Load Circuit

Figure 12 illustrates the load circuit used to test the
80960KA’s three-state pins; Figure 13 shows the load
circuit used to test the open drain outputs. The open
drain test uses an active load circuit in the form of a
matched diode bridge. Since the open-drain outputs
sink current, only the I

OL

legs of the bridge are

necessary and the I

OH

legs are not used. When the
80960KA driver under test is turned off, the output pin
is pulled up to V

REF

(i.e., VOH). Diode D1 is turned off

and the I

OL

current source flows through diode D2.

When the 80960KA open-drain driver under test is
on, diode D

1

is also on and the voltage on the pin

being tested drops to V

OL

. Diode D2 turns off and I

OL

flows through diode D1.

Figure 12. Test Load Circuit for Three-State Output Pins

Figure 13. Test Load Circuit for Open-Drain Output Pins

THREE-STATE OUTPUT

C

L

= 50 pF for all signals

C

L

C

L

OPEN-DRAIN OUTPUT

I

OL

D

2

IOL Tested at 25 mA
V

REF

= V

CC

D1 and D2 are matched

D

1

CL = 50 pF for all signals

80960KA

15

2.7. DC Characteristics

2.6. Absolute Maximum Ratings

NOTICE: This is a production data sheet. The specifi­cations are subject to change without notice.

Operating Temperature (PGA).............. 0°C to +85°C Case

(PQFP) ......... 0°C to +100°C Case

Storage Temperature ................................. –65°C to +150°C

Voltage on Any Pin................................. –0.5V to V

CC

+0.5V

Power Dissipation .......................................... 2.5W (25 MHz)

*WARNING: Stressing the device beyond the “Absolute Maxi­mum Ratings” may cause permanent damage. These are
stress ratings only. Operation beyond the “Operating Condi­tions” is not recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.

PGA: 80960KA (16 MHz) T

CASE

= 0°C to +85°C, VCC = 5V ± 10%

80960KA (20 and 25 MHz) T

CASE

= 0°C to +85°C, VCC = 5V ± 5%

PQFP: 80960KA (16 MHz) T

CASE

= 0°C to +100°C, VCC = 5V ± 10%

80960KA (20 and 25 MHz) T

CASE

= 0°C to +100°C, VCC = 5V ± 5%

Table 5. DC Characteristics

Symbol Parameter Min Max Units Notes

V

IL

Input Low Voltage –0.3 +0.8 V

V

IH

Input High Voltage 2.0 VCC + 0.3 V

V

CL

CLK2 Input Low Voltage –0.3 +0.8 V

V

CH

CLK2 Input High Voltage 0.55 V

CC

VCC + 0.3 V

V

OL

Output Low Voltage 0.45 V (1,2)

V

OH

Output High Voltage 2.4 V (3,4)

I

CC

Power Supply Current:

16 MHz
20 MHz
25 MHz

315
360
420

mA
mA
mA

(5)
(5)
(5)

I

LI

Input Leakage Current ±15 µA 0 ≤ VIN≤ V

CC

I

LO

Output Leakage Current ±15 µA 0.45 ≤ VO≤ V

CC

C

IN

Input Capacitance 10 pF fC = 1 MHz (6)

C

O

Output Capacitance 12 pF fC = 1 MHz (6)

C

CLK

Clock Capacitance 10 pF fC = 1 MHz (6)

NOTES:

1. For three-state outputs, this parameter is measured at:

Address/Data............................................................................................................................................................................................. 4.0 mA

Controls ......................................................................................................................................................................................................5.0 mA

2. For open-drain outputs ................................................................................................................................................................................ 25 mA

3. This parameter is measured at:

Address/Data ........................................................................................................................................................................................... -1.0 mA

Controls .................................................................................................................................................................................................... -0.9 mA

ALE

.......................................................................................................................................................................................................... -5.0 mA

4. Not measured on open-drain outputs.

5. Measured at worst case frequency, V

CC

and temperature, with device operating and outputs loaded to the test conditions in Figures 12 and 13.

Figure 7, Figure 8 and Figure 9 indicate typical values.

6. Input, output and clock capacitance are not tested.

80960KA

16

2.8. AC Specifications

This section describes the AC specifications for the
80960KA pins. All input and output timings are
specified relative to the 1.5 V level of the rising edge
of CLK2. For output timings the specifications refer to
the time it takes the signal to reach 1.5 V.

For input timings the specifications refer to the time at
which the signal reaches (for input setup) or leaves
(for hold time) the TTL levels of LOW (0.8 V) or HIGH
(2.0 V). All AC testing should be done with input
voltages of 0.4 V and 2.4 V, except for the clock
(CLK2), which should be tested with input voltages of

0.45 V and 0.55 V

CC

.

Figure 14. Drive Levels and Timing Relationships for 80960KA Signals

A B C

D

A

B C

1.5V 1.5V 1.5V 1.5V

0.8V

T

6

1.5V

1.5V

T

7

1.5V

1.5V

VALID OUTPUT

T

6

T

8

T

8

T

13

T

14

1.5V 1.5V

VALID OUTPUT

T

9

2.0V 2.0V

2.0V 2.0V

0.8V 0.8V

0.8V 0.8V

EDGE

CLK2

OUTPUTS:

LAD 31:0
ADS
W/R, DEN
BE3:0
HLDA
CACHE
LOCK

, INTA

ALE

DT/R

INPUTS:

LAD31:0
BADAC
IAC/INT0, INT1
INT2/INTR, INT3

HOLD
LOCK
READY

T

9

VALID INPUT

T

10

T

11

T

12

T

11

80960KA

17

2.8.1. AC Specification Tables

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I

LO

. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC

, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.

Table 6. 80960KA AC Characteristics (16 MHz)

Symbol Parameter Min Max Units Notes

Input Clock
T

1

Processor Clock Period (CLK2) 31.25 125 ns VIN = 1.5V

T

2

Processor Clock Low Time (CLK2) 8 ns VIL = 10% Point = 1.2V

T

3

Processor Clock High Time
(CLK2)

8 ns VIH = 90% Point = 0.1V + 0.5 V

CC

T

4

Processor Clock Fall Time (CLK2) 10 ns VIN = 90% Point to 10% Point (1)

T

5

Processor Clock Rise Time (CLK2) 10 ns VIN = 10% Point to 90% Point (1)

Synchronous Outputs
T

6

Output Valid Delay 2 25 ns

T

6H

HLDA Output Valid Delay 4 28 ns

T

7

ALE Width 15 ns

T

8

ALE Output Valid Delay 2 18 ns

T

9

Output Float Delay 2 20 ns (2)

T

9H

HLDA Output Float Delay 4 20 ns (2)

Synchronous Inputs
T

10

Input Setup 1 3 ns (3)

T

11

Input Hold 5 ns (3)

T

11H

HOLD Input Hold 4 ns (3)

T

12

Input Setup 2 8 ns (3)

T

13

Setup to ALE Inactive 10 ns

T

14

Hold after ALE Inactive 8 ns

T

15

Reset Hold 3 ns (3)

T

16

Reset Setup 5 ns (3)

T

17

Reset Width 1281 ns 41 CLK2 Periods Minimum

NOTES:

80960KA

18

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I

LO

. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC

, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.

Table 7. 80960KA AC Characteristics (20 MHz)

Symbol Parameter Min Max Units Notes

Input Clock
T

1

Processor Clock Period (CLK2) 25 125 ns VIN = 1.5V

T

2

Processor Clock Low Time (CLK2) 6 ns VIL = 10% Point = 1.2V

T

3

Processor Clock High Time
(CLK2)

6 ns VIH = 90% Point = 0.1V + 0.5 V

CC

T

4

Processor Clock Fall Time (CLK2) 10 ns VIN = 90% Point to 10% Point (1)

T

5

Processor Clock Rise Time (CLK2) 10 ns VIN = 10% Point to 90% Point (1)
Synchronous Outputs
T

6

Output Valid Delay 2 20 ns
T

6H

HLDA Output Valid Delay 4 23 ns
T

7

ALE Width 12 ns
T

8

ALE Output Valid Delay 2 18 ns
T

9

Output Float Delay 2 20 ns (2)
T

9H

HLDA Output Float Delay 4 20 ns (2)
Synchronous Inputs

T

10

Input Setup 1 3 ns (3)
T

11

Input Hold 5 ns (3)
T

11H

HOLD Input Hold 4 ns (3)
T

12

Input Setup 2 7 ns (3)
T

13

Setup to ALE Inactive 10 ns
T

14

Hold after ALE Inactive 8 ns
T

15

Reset Hold 3 ns
T

16

Reset Setup 5 ns
T

17

Reset Width 1025 ns 41 CLK2 Periods Minimum

NOTES:

80960KA

19

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I

LO

. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC

, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.

Table 8. 80960KA AC Characteristics (25 MHz)

Symbol Parameter Min Max Units Notes

Input Clock
T

1

Processor Clock Period (CLK2) 20 125 ns VIN = 1.5V
T

2

Processor Clock Low Time (CLK2) 5 ns VIL = 10% Point = 1.2V
T

3

Processor Clock High Time

(CLK2)

5 ns VIH = 90% Point = 0.1V + 0.5 V

CC

T

4

Processor Clock Fall Time (CLK2) 10 ns VIN = 90% Point to 10% Point (1)
T

5

Processor Clock Rise Time (CLK2) 10 ns VIN = 10% Point to 90% Point (1)
Synchronous Outputs
T

6

Output Valid Delay 2 18 ns
T

6H

HLDA Output Valid Delay 4 23 ns
T

7

ALE Width 12 ns
T

8

ALE Output Valid Delay 2 18 ns
T

9

Output Float Delay 2 18 ns (2)
T

9H

HLDA Output Float Delay 4 20 ns (2)
Synchronous Inputs

T

10

Input Setup 1 3 ns (3)
T

11

Input Hold 5 ns (3)
T

11H

HOLD Input Hold 4 ns
T

12

Input Setup 2 7 ns
T

13

Setup to ALE Inactive 8 ns
T

14

Hold after ALE Inactive 8 ns
T

15

Reset Hold 3 ns
T

16

Reset Setup 5 ns
T

17

Reset Width 820 ns 41 CLK2 Periods Minimum

NOTES:

80960KA

20

Figure 15. Processor Clock Pulse (CLK2)

Figure 16. RESET Signal Timing

HIGH LEVEL (MIN) 0.55V

CC

LOW LEVEL (MAX) 0.8V

T

1

T

3

T

5

T

4

T

2

90%

10%

1.5 V

...

...
...

...

CLK2

CLK

RESET

OUTPUTS

FIRST
A B C D A

INIT PARAMETERS (BADAC

,

INT

0

/IAC) MUST BE SET UP 8 CLOCKS

PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD

BEYOND THIS CLK2 EDGE

T15 = RESET HOLD
T

16

= RESET SETUP

T

17

= RESET WIDTH

T

15

T

16

T

17

80960KA

21

3.0 MECHANICAL DATA

3.1. Packaging

The 80960KA is available in two package types:

• 132-lead ceramic pin-grid array (PGA). Pins are
arranged 0.100 inch (2.54 mm) center-to-center, in
a 14 by 14 matrix, three rows around (see Figure

17).

• 132-lead plastic quad flat pack (PQFP). This
package uses fine-pitch gull wing leads arranged in
a single row along the package perimeter with

0.025 inch (0.64 mm) spacing (see Figure 20).

Dimensions for both package types are given in the
Intel Packaging handbook (Order #240800).

3.1.1. Pin Assignment

The PGA and PQFP have different pin assignments.
Figure 18 shows the view from the PGA bottom (pins
facing up) and Figure 19 shows a view from the PGA
top (pins facing down). Figure 20 shows the PQFP
package; Figure 21 shows the PQFP pinout with
signal names. Notice that the pins are numbered in
order from 1 to 132 around the package perimeter.
Table 9 and Table 10 list the function of each PGA
pin; Table 11 and Table 12 list the function of each
PQFP pin.

Figure 17. 132-Lead Pin-Grid Array (PGA) Package

1
2
3

A B C D E F G H J K L M N P

4
5
6
7
8

9
10
11
12
13

14

80960KA

22

Figure 18. 80960KA PGA Pinout—View from Bottom (Pins Facing Up)

V

CC

V

SS

N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.V

CC

N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.V

SS

N.C.V

CC

N.C.

V

CC

V

SS

N.C.N.C.N.C.N.C.

V

CC

V

SS

N.C.N.C.

V

SS

V

CC

N.C.DEN

V

SS

FAILBE

3

V

SS

BE

2

DT/R

LOCKBE

0

W/R

BE

1

READYLAD

30

CACHE

LAD

31

LAD

29

LAD

27

LAD

26

LAD

28

HLDAADSALE

N.C.N.C.

N.C.N.C.

N.C.N.C.N.C.

N.C.N.C.N.C.

N.C.N.C.N.C.

N.C.N.C.N.C.

N.C.N.C.

N.C.N.C.

V

SS

V

CC

V

SS

V

CC

V

SS

V

SS

V

SS

V

SS

V

CC

V

CC

V

CC

V

CC

INT

2

INT

0

INT

1

INT

3

LAD

3

LAD

8

LAD

20

LAD

13

BADACHOLD LAD

25

RESETLAD

0

LAD

1

LAD

4

LAD

5

LAD

7

LAD

9

LAD

11

LAD

14

LAD

16

LAD

17

LAD

19

LAD

2

LAD

6

LAD

10

LAD

12

LAD

15

LAD

18

LAD

21

LAD

22

LAD

24

LAD

23

CLK2

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1413121110987654321

1413121110987654321

80960KA

23

Figure 19. 80960KA PGA Pinout—View from Top (Pins Facing Down)

Figure 20. 80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package

VCCVSSN.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V

CC

N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

N.C.

N.C. N.C.

V

SS

N.C. N.C. N.C.

V

CCVSS

N.C. N.C. N.C. N.C.

V

CCVSS

VCCN.C.

V

SS

VCCN.C. DEN

V

SS

FAIL BE

3

VSSBE2DT/R

LOCK BE

0

W/R

BE

1

READY LAD

30

CACHE LAD31LAD

29

LAD27LAD26LAD

28

HLDA ADS ALE

N.C. N.C.

N.C. N.C.

N.C. N.C. N.C.

N.C. N.C. N.C.

N.C. N.C. N.C.

N.C. N.C. N.C.

N.C. N.C.

N.C. N.C.

V

SS

V

CC

V

SS

V

CC

V

SS

V

SS

V

SS

VSSV

CC

V

CC

V

CC

VCCINT

2

INT0INT1INT

3

LAD3LAD

8

LAD

20

LAD

13

BADAC HOLDLAD

25

RESET LAD

0

LAD1LAD4LAD5LAD7LAD9LAD11LAD14LAD16LAD17LAD

19

LAD2LAD6LAD10LAD12LAD15LAD18LAD21LAD22LAD24LAD

23

CLK2

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

14 13 12 11 10 9 8 7 6 5 4 3 2 1

14 13 12 11 10 9 8 7 6 5 4 3 2 1

A80960KA-25

XXXXXXXX

XXXXXX

XXXXXX

80960KA

24

Figure 21. PQFP Pinout - View From Top

LAD0
LAD1
LAD2

V

SS

LAD3
LAD4

LAD5
LAD6
LAD7
LAD8

LAD9
LAD10
LAD11
LAD12

V

SS

LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22

V

SS

LAD23
LAD24
LAD25

BADAC

HOLD

NC

ADS

VSSNCNCNCNCNC

RESET

VCCCLK2

VSSNC

INT3/INTA

INT2/INTR

INT1

IAC/INT0

V

SSVCC

VCCNC

V

SS

V

SS

NCNCNC

NC

VCCV

SS

NC

V

CC

VCCNC

V

SS

V

SS

NC
NC
NC
NC
NC
NC
NC
NC
NC
V

SS

V

CC

V

CC

NC
V

SS

V

SS

NC
NC

NC
NC
NC
NC
NC
NC
NC
V

SS

V

CC

NC
NC
NC
NC
V

CC

V

CC

NC

HLDA

ALE

LAD26

LAD27

LAD28

LAD29

LAD30

LAD31

V

SS

CACHE

W/R

READY

DT/R

BE0

BE1

BE2

BE3

FAILURE

V

SS

LOCK

DEN

VSSV

SS

NC

NC

VSSV

SS

NC

VCCV

CC

NC

VSSV

SS

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

1 2 3

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

99 98 97

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67

NG80960KA-25

XXXXXXXX

XXXXXX

XXXXXX

80960KA

25

3.2. Pinout

NOTE: Do not connect any external logic to any pins marked N.C.

Table 9. 80960KA PGA Pinout — In Pin Order

Pin Signal Pin Signal Pin Signal Pin Signal

A1 V

CC

C6 LAD

20

H1 W/R M10 V

SS

A2 V

SS

C7 LAD

13

H2 BE

0

M11 V

CC

A3 LAD

19

C8 LAD

8

H3 LOCK M12 N.C.

A4 LAD

17

C9 LAD

3

H12 N.C. M13 N.C.

A5 LAD

16

C10 V

CC

H13 N.C. M14 N.C.

A6 LAD

14

C11 V

SS

H14 N.C. N1 V

SS

A7 LAD

11

C12 INT3/INTA J1 DT/R N2 N.C.

A8 LAD

9

C13 INT

1

J2 BE

2

N3 N.C.

A9 LAD

7

C14 IAC/INT

0

J3 V

SS

N4 N.C.

A10 LAD

5

D1 ALE J12 N.C. N5 N.C.

A11 LAD

4

D2 ADS J13 N.C. N6 N.C.

A12 LAD

1

D3 HLDA J14 N.C. N7 N.C.

A13 INT

2

/INTR D12 V

CC

K1 BE

3

N8 N.C.

A14 V

CC

D13 N.C. K2 FAILURE N9 N.C.

B1 LAD

23

D14 N.C. K3 V

SS

N10 N.C.

B2 LAD

24

E1 LAD

28

K12 V

CC

N11 N.C.

B3 LAD

22

E2 LAD

26

K13 N.C. N12 N.C.

B4 LAD

21

E3 LAD

27

K14 N.C. N13 N.C.

B5 LAD

18

E12 N.C. L1 DEN N14 N.C.

B6 LAD

15

E13 V

SS

L2 N.C. P1 V

CC

B7 LAD

12

E14 N.C. L3 V

CC

P2 N.C.

B8 LAD

10

F1 LAD

29

L12 V

SS

P3 N.C.

B9 LAD

6

F2 LAD

31

L13 N.C. P4 N.C.

B10 LAD

2

F3 CACHE L14 N.C. P5 N.C.
B11 CLK2 F12 N.C. M1 N.C. P6 N.C.
B12 LAD

0

F13 N.C. M2 V

CC

P7 N.C.

B13 RESET F14 N.C. M3 V

SS

P8 N.C.

B14 V

SS

G1 LAD

30

M4 V

SS

P9 N.C.

C1 HOLD G2 READY

M5 V

CC

P10 N.C.

C2 LAD

25

G3 BE

1

M6 N.C. P11 N.C.

C3 BADAC

G12 N.C. M7 N.C. P12 N.C.
C4 V

CC

G13 N.C. M8 N.C. P13 V

SS

C5 V

SS

G14 N.C. M9 N.C. P14 V

CC

80960KA

26

NOTE: Do not connect any external logic to any pins marked N.C.

Table 10. 80960KA PGA Pinout — In Signal Order

Signal Pin Signal Pin Signal Pin Signal Pin

ADS

D2 LAD

15

B6 N.C. J14 N.C. P9

ALE

D1 LAD

16

A5 N.C. K13 N.C. P10

BADAC

C3 LAD

17

A4 N.C. K14 N.C. P11

BE

0

H2 LAD

18

B5 N.C. L13 N.C. P12

BE

1

G3 LAD

19

A3 N.C. L14 N.C. L2

BE

2

J2 LAD

20

C6 N.C. M1 READY G2

BE

3

K1 LAD

21

B4 N.C. M6 RESET B13

CACHE F3 LAD

22

B3 N.C. M7 V

CC

A1

CLK2 B11 LAD

23

B1 N.C. M8 V

CC

A14

DEN

L1 LAD

24

B2 N.C. M9 V

CC

C4

DT/R

J1 LAD

25

C2 N.C. M12 V

CC

C10

FAILURE

K2 LAD

26

E2 N.C. M13 V

CC

D12

HLDA D3 LAD

27

E3 N.C. M14 V

CC

K12

HOLD C1 LAD

28

E1 N.C. N2 V

CC

L3

IAC

/INT

0

C14 LAD

29

F1 N.C. N3 V

CC

M2

INT

1

C13 LAD

30

G1 N.C. N4 V

CC

M5

INT

2

/INTR A13 LAD

31

F2 N.C. N5 V

CC

M11

INT

3

/INTA C12 LOCK H3 N.C. N6 V

CC

P1

LAD

0

B12 N.C. D13 N.C. N7 V

CC

P14

LAD

1

A12 N.C. D14 N.C. N8 V

SS

A2

LAD

2

B10 N.C. E12 N.C. N9 V

SS

B14

LAD

3

C9 N.C. E14 N.C. N10 V

SS

C5

LAD

4

A11 N.C. F12 N.C. N11 V

SS

C11

LAD

5

A10 N.C. F13 N.C. N12 V

SS

E11

LAD

6

B9 N.C. F14 N.C. N13 V

SS

J3

LAD

7

A9 N.C. G12 N.C. N14 V

SS

K3

LAD

8

C8 N.C. G13 N.C. P2 V

SS

L12

LAD

9

A8 N.C. G14 N.C. P3 V

SS

M3

LAD

10

B8 N.C. H12 N.C. P4 V

SS

M4

LAD

11

A7 N.C. H13 N.C. P5 V

SS

M10

LAD

12

B7 N.C. H14 N.C. P6 V

SS

N1

LAD

13

C7 N.C. J12 N.C. P7 V

SS

P13

LAD

14

A6 N.C. J13 N.C. P8 W/R H1

80960KA

27

NOTE: Do not connect any external logic to any pins marked N.C.

Table 11. 80960KA PQFP Pinout — In Pin Order

Pin Signal Pin Signal Pin Signal Pin Signal
1 HLDA 34 N.C. 67 V

SS

100 LAD

0

2 ALE 35 V

CC

68 V

SS

101 LAD

1

3 LAD

26

36 V

CC

69 N.C. 102 LAD

2

4 LAD

27

37 N.C. 70 V

CC

103 V

SS

5 LAD

28

38 N.C. 71 V

CC

104 LAD

3

6 LAD

29

39 N.C. 72 N.C. 105 LAD

4

7 LAD

30

40 N.C. 73 V

SS

106 LAD

5

8 LAD

31

41 V

CC

74 V

CC

107 LAD

6

9 V

SS

42 V

SS

75 N.C. 108 LAD

7

10 CACHE 43 N.C. 76 N.C. 109 LAD

8

11 W/R 44 N.C. 77 N.C. 110 LAD

9

12 READY 45 N.C. 78 N.C. 111 LAD

10

13 DT/R 46 N.C. 79 V

SS

112 LAD

11

14 BE

0

47 N.C. 80 V

SS

113 LAD

12

15 BE

1

48 N.C. 81 N.C. 114 V

SS

16 BE

2

49 N.C. 82 V

CC

115 LAD

13

17 BE

3

50 N.C. 83 V

CC

116 LAD

14

18 FAILURE 51 N.C. 84 V

SS

117 LAD

15

19 V

SS

52 V

SS

85 IAC/INT

0

118 LAD

16

20 LOCK 53 V

SS

86 INT

1

119 LAD

17

21 DEN 54 N.C. 87 INT2/INTR 120 LAD

18

22 V

SS

55 V

CC

88 INT3/INTA 121 LAD

19

23 V

SS

56 V

CC

89 N.C. 122 LAD

20

24 N.C. 57 V

SS

90 V

SS

123 LAD

21

25 N.C. 58 N.C. 91 CLK2 124 LAD

22

26 V

SS

59 N.C. 92 V

CC

125 V

SS

27 V

SS

60 N.C. 93 RESET 126 LAD

23

28 N.C. 61 N.C. 94 N.C. 127 LAD

24

29 V

CC

62 N.C. 95 N.C. 128 LAD

25

30 V

CC

63 N.C. 96 N.C. 129 BADAC
31 N.C. 64 N.C. 97 N.C. 130 HOLD
32 V

SS

65 N.C. 98 N.C. 131 N.C.
33 V

SS

66 N.C. 99 V

SS

132 ADS

80960KA

28

NOTE: Do not connect any external logic to any pins marked N.C.

Table 12. 80960KA PQFP Pinout — In Signal Order

Signal Pin Signal Pin Signal Pin Signal Pin

ADS

132 LAD

15

117 N.C. 49 V

CC

41

ALE

2 LAD

16

118 N.C. 50 V

CC

55

BADAC

129 LAD

17

119 N.C. 51 V

CC

56

BE

0

14 LAD

18

120 N.C. 54 V

CC

70

BE

1

15 LAD

19

121 N.C. 58 V

CC

71

BE

2

16 LAD

20

122 N.C. 59 V

CC

74

BE

3

17 LAD

21

123 N.C. 60 V

CC

82

CACHE 10 LAD

22

124 N.C. 61 V

CC

83

CLK2 91 LAD

23

126 N.C. 62 V

CC

92

DEN

21 LAD

24

127 N.C. 63 V

SS

9

DT/R

13 LAD

25

128 N.C. 64 V

SS

19

FAILURE

18 LAD

26

3 N.C. 65 V

SS

22

HLDA 1 LAD

27

4 N.C. 66 V

SS

23

HOLD 130 LAD

28

5 N.C. 69 V

SS

26

IAC

/INT

0

85 LAD

29

6 N.C. 72 V

SS

27

INT

1

86 LAD

30

7 N.C. 75 V

SS

32

INT

2

/INTR 87 LAD

31

8 N.C. 76 V

SS

33

INT

3

/INTA 88 LOCK 20 N.C. 77 V

SS

42

LAD

0

100 N.C. 24 N.C. 78 V

SS

52

LAD

1

101 N.C. 25 N.C. 81 V

SS

53

LAD

2

102 N.C. 28 N.C. 89 V

SS

57

LAD

3

104 N.C. 31 N.C. 94 V

SS

67

LAD

4

105 N.C. 34 N.C. 95 V

SS

68

LAD

5

106 N.C. 37 N.C. 96 V

SS

73

LAD

6

107 N.C. 38 N.C. 97 V

SS

79

LAD

7

108 N.C. 39 N.C. 98 V

SS

80

LAD

8

109 N.C. 40 N.C. 131 V

SS

84

LAD

9

110 N.C. 43 READY 12 V

SS

90

LAD

10

111 N.C. 44 RESET 93 V

SS

99

LAD

11

112 N.C. 45 V

CC

29 V

SS

103

LAD

12

113 N.C. 46 V

CC

30 V

SS

114

LAD

13

115 N.C. 47 V

CC

35 V

SS

125

LAD

14

116 N.C. 48 V

CC

36 W/R 11

80960KA

29

3.3. Package Thermal Specification

The 80960KA is specified for operation when case
temperature is within the range 0°C to 85°C (PGA) or
0°C to 100°C (PQFP). Measure case temperature at
the top center of the package. Ambient temperature
can be calculated from:

T

J

= TC + P*θ

jc

TA = TJ + P*θ

ja

TC = TA + P*[θja−θjc]
Values for

θja and θjc for various airflows are given in

Table 13 for the PGA package and in Table 14 for the
PQFP package. The PGA’s

θja can be reduced by

adding a heatsink. For the PQFP, however, a heatsink
is not generally used since the device is intended to
be surface mounted.

Maximum allowable ambient temperature (T

A

)

permitted without exceeding T

C

is shown by the
graphs in Figures 23, 24, 25 and 26. The curves
assume the maximum permitted supply current (I

CC

)

at each speed, V

CC

of +5.0 V and a T

CASE

of +85°C

(PGA) or +100°C (PQFP).
If the 80960KA is to be used in a harsh environment

where the ambient temperature may exceed the limits
for the normal commercial part, consider using an
extended temperature device. These components are
designated by the prefix “TA” and are available at 16,
20 and 25 MHz in the ceramic PGA package.
Extended operating temperature range is –40° C to
+125°C (case).

Figure 26 shows the maximum allowable ambient
temperature for the 20 MHz extended temperature
TA80960KA at various airflows. The curve assumes
an I

CC

of 420 mA, VCC of 5.0 V and a T

CASE

of

+125°C.

Table 13. 80960KA PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)50(0.25)

100

(0.50)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

θ Junction-to-Case

2 2 2 2 2 2 2

θ Case-to-Ambient

(No Heatsink)

19 18 17 15 12 10 9

θ Case-to-Ambient

(Omnidirectional
Heatsink)

16 15 14 12 9 7 6

θ Case-to-Ambient

(Unidirectional
Heatsink)

15 14 13 11 8 6 5

NOTES:

1. This table applies to 80960KA PGA plugged into
socket or soldered directly to board.

2.

θ

JA

= θJC + θ

CA

3. θ

J-CAP

= 4°C/W (approx.)

θ

J-PIN

= 4°C/W (inner pins) (approx.)

θ

J-PIN

= 8°C/W (outer pins) (approx.)

θ

JC

θ

JA

θ

J-PIN

θ

J-CAP

80960KA

30

Figure 22. HOLD Timing

Table 14. 80960KA PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)50(0.25)

100

(0.50)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

θ Junction-to-Case

9 9 9 9 9 9 9

θ Case-to-Ambient

(No Heatsink)

22 19 18 16 11 9 8

NOTES:

1. This table applies to 80960KA PQFP soldered

directly to board.

2.

θ

JA

= θJC + θ

CA

3. θJL = 18°C/W (approx.)

θ

JB

= 18°C/W (approx.)

θ

JC

θ

JL

θ

JB

T

h

T

h

T

h

CLK2

CLK

HOLD

HLDA

T

12

T

11

T

6H

T

9H

80960KA

31

Figure 23. 16 MHz Maximum Allowable Ambient Temperature

Figure 24. 20 MHz Maximum Allowable Ambient Temperature

85
80
75
70
65
60
55

0 200 400 600 800

PQFP PGA with no

heatsink

PGA with omni­directional heatsink

PGA with uni­directional heatsink

AIRFLOW (ft/min)

TEMPERATURE(

o

C)

90

90
85
80
75
70
65
60

0 200 400 600 800

PQFP PGA with no

heatsink

PGA with omni­directional heatsink

PGA with uni­directional heatsink

AIRFLOW (ft/min)

TEMPERATURE(

o

C)

55
50

80960KA

32

Figure 25. 25 MHz Maximum Allowable Ambient Temperature

Figure 26. Maximum Allowable Ambient Temperature

for the Extended Temperature TA-80960KA at 20 MHz in PGA Package

AIRFLOW (ft/min)

TEMPERATURE(

o

C)

80
75
70
65
60
55

50
45
40

0 100 200 300 400 500 600 700 800

PQFP PGA with no

heatsink

PGA with omni­directional heatsink

PGA with uni­directional heatsink

85

PGA with no
heatsink

PGA with omni­directional heatsink

AIRFLOW (ft/min)

TEMPERATURE (

o

C)

0 100 200 300 400 500 600 700 800

120

115

110

105

100

95

90

PGA with uni­directional heatsink

80960KA

33

4.0 WAVEFORMS

Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KA’s local bus.

Figure 27. Non-Burst Read and Write Transactions Without Wait States

T

a

T

d

T

r

T

a

T

d

T

r

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

80960KA

34

Figure 28. Burst Read and Write Transaction Without Wait States

T

a

T

d

T

d

T

r

T

a

T

d

T

d

T

d

T

d

T

r

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

80960KA

35

Figure 29. Burst Write Transaction with 2, 1, 1, 1 Wait States

T

a

T

w

T

w

T

d

T

w

T

d

T

w

T

d

T

w

T

d

T

r

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

80960KA

36

Figure 30. Accesses Generated by Quad Word Read Bus Request,

Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)

T

a

T

w

T

d

T

d

T

d

T

d

T

r

T

a

T

w

T

d

T

r

CLK2

CLK

LAD31:0

ALE

ADS

BE3:2

W/R

DT/R

DEN

READY

BE1:0

80960KA

37

Figure 31. Interrupt Acknowledge Transaction

CLK2

T

X

TXTaT

d

T

r

T

r

TIT

I

TIT

I

TITaT

w

T

d

INTR

LAD31:0

ALE

ADS

INTA

DT/R

DEN

LOCK

READY

NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.

For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 1

IDLE

(5 BUS STATES)

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 2

PREVIOUS

CYCLE

ADDR

VECTOR

ADDR

CLK

80960KA

38

5.0 REVISION HISTORY

No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to
date is incorporated into this revision. The sections significantly changed since the previous revision are:

Section

Last
Rev.

Description

Table 3. 80960KA Pin Description:
L-Bus Signals (pg. 8)

-004 LOCK

pin description rewritten for clarity.

2.3. Connection Recommenda-

tions (pg. 11)

-004 Changed suggested open-drain termination networks to
reflect more realistic operating conditions with reduction in
DC power consumption.

Figure 9. Typical Current vs. Fre­quency (Hot Temp) (pg. 13)

-004 Added figure for typical power supply current at hot tempera­ture to aid thermal analysis.

Figure 12. Test Load Circuit for
Three-State Output Pins (pg. 14)

Figure 13. Test Load Circuit for
Open-Drain Output Pins (pg. 14)

-004 All outputs now specified with standard 50 pF test loads to
agree with actual test methodology.

2.7. DC Characteristics (pg. 15) -004 ICC max specification reduced:

WAS: IS: AT:

375 mA 315 mA 16 MHz
420 mA 360 mA 20 MHz
480 mA 420 mA 25 MHz

Figures 7, 8, 9, 23, 24, 25 and 26 have also been changed
accordingly.

2.8. AC Specifications (pg. 16) -004 25 MHz operation extended to product in PQFP package. T

8

min. improved at all frequencies from 0 ns to 2 ns and T

8

max. improved from 20 ns to 18 ns.
T

8H

max improvement:

WAS: IS: AT:

31ns 28ns 16 MHz
26ns 23ns 20 MHz
24ns 23ns 25 MHz

Functional Waveforms -004 Redrawn for clarity. CLK signal drawn with more likely phase

relationship to CLK2. Open-drain output signals drawn to
show correct inactive states.

Various -004 Deleted all references to 10 MHz. Intel no longer offers a

10 MHz 80960KA device.

80960KA

39

80960KA

40