Page 1
NDT014
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
September 1996
Power SOT N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
2.7A, 60V. R
High density cell design for extremely low R
= 0.2Ω @ VGS = 10V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
_________________________________________________________________________________________________________
D
G
D S
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT014 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 60 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) ±2.7 A
- Pulsed ±10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT014 Rev. C1
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = 60 V, V
VDS = 48 V, V
= 0 V
GS
= 0 V, TJ=125°C 250 µA
GS
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
25 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 1.6 A
VDS = 25 V, ID = 1.6 A
2 3 4 V
0.18 0.2
2 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 60 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 15 pF
155 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD =30 V, ID = 10 A,
V
= 10 V, R
Turn - On Rise Time 64 100 ns
GEN
GEN
= 24 Ω
10 20 ns
Turn - Off Delay Time 10 20 ns
Turn - Off Fall Time 10 20 ns
Total Gate Charge VDS = 48 V,
Gate-Source Charge 1.2 3.1 nC
ID = 10 A, VGS = 10 V
5 11 nC
Gate-Drain Charge 2 5.8 nC
NDT014 Rev. C1
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
t
rr
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.7 A
Maximum Pulsed Drain-Source Diode Forward Current 22 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.7A
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
2
= I
(t) × R
DS(O N ) T
D
(t)
J
1a
VGS = 0 V, IF = 10 A, dIF/dt = 100 A/µs
1b
(Note 2) 0.95 1.6 V
1c
140 ns
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT014 Rev. C1
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I , DRAIN-CURRENT(A)
DRAIN-SOURCE ON-RESISTANCE
D
Typical Electrical Characteristics
8
6
V = 10V
GS
8.0
7.0
6.5
4
6.0
5.5
2
D
I , DRAIN-SOURCE CURRENT (A)
0
0 1 2 3 4
V , DRAIN-SOURCE VOLTAGE (V)
DS
5.0
4.5
2.5
V = 5.5V
GS
2
6.0
6.5
7.0
1.5
DS(on)
1
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
0 2 4 6 8 10
I , DRAIN CURRENT (A)
D
8.0
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate Voltage
and Drain Current.
2
I = 2.7A
D
1.8
V = 10V
GS
1.6
1.4
1.2
1
DS(ON)
R , NORMALIZED
0.8
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
3
V = 10 V
GS
2.5
T = 125°C
2
1.5
1
DS(ON)
R , NORMALIZED
0.5
0
0 2 4 6 8 10
J
25°C
-55°C
10
Figure 3. On-Resistance Variation
with Temperature.
10
V = 10V
DS
8
6
4
D
I , DRAIN CURRENT (A)
2
0
2 4 6 8 10
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
25°C
Figure 5. Transfer Characteristics.
125°C
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
1.2
V = V
1.1
1
0.9
th
V , NORMALIZED
0.8
GATE-SOURCE THRESHOLD VOLTAGE
0.7
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
DS GS
I = 250µA
D
Figure 6. Gate Threshold Variation with
Temperature.
NDT014 Rev. C1
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Typical Electrical Characteristics (continued)
1.15
I = 250µA
D
1.1
1.05
1
DSS
BV , NORMALIZED
0.95
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.9
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation with
Temperature.
400
300
200
100
50
30
CAPACITANCE (pF)
f = 1 MHz
V = 0V
20
GS
10
0.1 0.2 0.5 1 2 5 10 20 50
V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
10
5
V = 0V
GS
1
0.5
T = 125°C
J
0.1
0.01
S
I , REVERSE DRAIN CURRENT (A)
0.001
0.2 0.4 0.6 0.8 1 1.2 1.4
V , BODY DIODE FORWARD VOLTAGE (V)
SD
25°C
-55°C
Figure 8. Body Diode Forward Voltage Variation with
Current and Temperature.
15
I = 2.7A
D
iss
oss
C
rss
12
9
6
3
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 1 2 3 4 5 6
Q , GATE CHARGE (nC)
g
V = 10V
DS
20V
40V
Figure 9. Capacitance Characteristics.
V
DD
V
IN
R
D
V
GS
R
GEN
G
S
Figure 11. Switching Test Circuit.
L
DUT
V
OUT
Figure 10. Gate Charge Characteristics.
t t
on off
t
d(on)
r
t
d(off)
90%
V
OUT
V
IN
10%
50%
10%
PULSE WIDTH
Figure 12. Switching Waveforms.
50%
90%
90%
10%
tt
f
INVERTED
NDT014 Rev. C1
Page 6
Typical Electrical Characteristics (continued)
4
3
V = 10V
DS
T = -55°C
J
25°C
125°C
2
1
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
0 2 4 6 8 10
I , DRAIN CURRENT (A)
D
Figure 13. Transconductance Variation with Drain
20
10
5
2
RDS(ON) LIMIT
1
0.5
V = 10V
0.1
D
I , DRAIN CURRENT (A)
0.05
0.01
0.1 0.2 0.5 1 2 5 10 30 60 100
GS
SINGLE PULSE
o
R = 42 C/W
θ
JA
T = 25°C
A
V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
10s
10ms
100ms
1s
Figure 14. Maximum Safe Operating Area.
1ms
Current and Temperature.
1
0.5
D = 0.5
0.2
0.2
0.1
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.05
0.02
0.01
Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 300
t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R = See Note 1 c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
θ
100us
θ
JA
1
JA
2
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
NDT014 Rev. C1
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TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
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2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
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FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
SuperSOT™-3
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UHC™
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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