Datasheet nds8435a Datasheet

NDS8435A

Single P-Channel Enhancement Mode Field Effect Transistor

General Description Features

March 1997

SO-8 P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer

-7.9 A, -30 V. R
R

High density cell design for extremely low R

= 0.023 Ω @ V

DS(ON)

= 0.035 Ω @ V

DS(ON)

= -10 V

GS

= -4.5V.

GS

DS(ON).

High power and current handling capability in a widely used
surface mount package.

power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.

___________________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS8435A Units

V

DSS

V

GSS

I

D

P

D

TJ,T

Drain-Source Voltage -30 V

Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a)

- Pulsed

-7.9 A

-25

Maximum Power Dissipation (Note 1a) 2.5 W

(Note 1b)

(Note 1c)

Operating and Storage Temperature Range -55 to 150 °C

STG

1.2
1

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W

NDS8435A Rev.C1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BV

I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current

VDS = -24 V, V

GS

= 0 V

TJ = 55°C

-1 µA

-10 µA

Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

I

g

D(on)

GS(th)

DS(ON)

FS

Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.3 -3 V

TJ = 125°C

-0.7 -1 -2.2

Static Drain-Source On-Resistance VGS = -10 V, ID = -7.9 A 0.02 0.023

0.027 0.041

0.03 0.035

-25 A

-10

-17 S

On-State Drain Current

Forward Transconductance

TJ = 125°C
VGS = -4.5 V, ID = -6.5 A
VGS = -10 V, VDS = -5 V
VGS = -4.5, VDS = -5 V
VDS = -10 V, ID = -7.9 A

Ω

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = -15 V, V
Output Capacitance 950 pF

f = 1.0 MHz

GS

= 0 V,

1800 pF

Reverse Transfer Capacitance 240 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

Turn - On Delay Time
Turn - On Rise Time 20 35 ns

VDD = -10 V, ID = -1 A,
V

= -10 V, R

GEN

GEN

= 6 Ω

Turn - Off Delay Time 95 180 ns
Turn - Off Fall Time 46 100 ns

g

gs

gd

Total Gate Charge
Gate-Source Charge 6 nC
Gate-Drain Charge 12 nC

VDS = -15 V,
ID = -7.9 A, VGS = -10 V

11 22 ns

48 67 nC

NDS8435A Rev.C1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Maximum Continuous Drain-Source Diode Forward Current -2.1 A
Drain-Source Diode Forward Voltage

VGS = 0 V, IS = -2.1 A

(Note 2)

-0.74 -1.2 V

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

design while R

(t)

P

D

Typical R

is determined by the user's board design.

CA

θ

T

T

J−TA

=

R

θJA

JA

θ

a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.

b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.

c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.

J−TA

=

(t)

R

θJC+RθCA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

2

= I

(t ) ×R

D

DS(O N ) T

(t)

J

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

1a

1b

1c

NDS8435A Rev.C1

Typical Electrical Characteristics

-30

V =-10V

-24

GS

-6.0

-4.5

-4.0

-3.5

-18

-12

-6

D

I , DRAIN-SOURCE CURRENT (A)

-3.0

-2.5

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.6

I = -7.9A

D

V = -10V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

2.5

V =-3.5V

GS

2

-4.0

1.5

DS(on)

1

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

-3-2.5-2-1.5-1-0.50

0.5

-4.5

-5.0

I , DRAIN CURRENT (A)

D

-6.0

-7.0

-10

-25-20-15-10-50

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

2

V = -10V

GS

1.5

1

DS(on)

R , NORMALIZED

0.5

DRAIN-SOURCE ON-RESISTANCE

0

T = 125°C

J

25°C

-55°C

I , DRAIN CURRENT (A)

D

-25-20-15-10-50

Figure 3. On-Resistance Variation

with Temperature.

-25

V = -10V

DS

-20

-15

-10

D

I , DRAIN CURRENT (A)

-5

0

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Charateristics.

T = -55°C

J

125°C

25°C

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

1.2

1.1

1

0.9

0.8

GS(th)

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE

-4-3.5-3-2.5-2-1.5-1

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

V = V

DS

GS

I =-250µA

D

Figure 6. Gate Threshold Variation

with Temperature.

NDS8435A Rev.C1

Typical Electrical Characteristics (continued)

1.125

1.1

I = -250µA

D

1.075

1.05

1.025

1

DSS

0.975

BV , NORMALIZED

0.95

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.925

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage

Variation with Temperature.

4000

3000

2000

1000

500

CAPACITANCE (pF)

f = 1 MHz

300

V = 0 V

GS

150

0.1 0.2 0.5 1 2 5 10 20 30

-V , DRAIN TO SOURCE VOLTAGE (V)
DS

C

C

C

rss

iss

oss

20

V = 0V

GS

5

1

0.1

0.01

0.001

S

-I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

T = 125°C

J

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation

with Source Current and

Temperature.

10

I = -7.9A

D

8

6

4

2

GS

-V , GATE-SOURCE VOLTAGE (V)

0

0 10 20 30 40 50

Q , GATE CHARGE (nC)

g

V = -5V

DS

-15

-10

Figure 9. Capacitance Characteristics.

-V

DD

V

IN

R

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit.

L

DUT

V

OUT

Figure 10. Gate Charge Characteristics.

t t

on off

t

d(on)

r

t

d(off)

90%

V

OUT

V

IN

10%

50%

10%

PULSE WIDTH

Figure 12. Switching Waveforms.

50%

10%

90%

tt

90%

INVERTED

NDS8435A Rev.C1

f

Typical Electrical and ThermalCharacteristics (continued)

40

V = - 10V

DS

32

24

T = -55°C

J

25°C

125°C

16

8

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

Figure 13. Transconductance Variation with Drain

Current and Temperature.

8.5

8

7.5

7

6.5

1b

6

1c

5.5

D

-I , STEADY-STATE DRAIN CURRENT (A)
5

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = -10V

GS

2

2.5

1a

2

1.5

1b

1c

1

STEADY-STATE POWER DISSIPATION (W)

-30-24-18-12-60

0.5
0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

2

Figure 14. SO-8 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad Area.

50
30

1a

10

RDS(ON) LIMIT

5

2

1

0.5

V = -10V

0.1

D

-I , DRAIN CURRENT (A)

0.05

0.01

0.1 0.2 0.5 1 2 5 10 20 30 50

GS

SINGLE PULSE

R = See Note 1c

JA

θ

A

T = 25°C

A

- V , DRAIN-SOURCE VOLTAGE (V)

DS

1s

10s

DC

100us

1ms

10ms

100ms

Figure 15. Maximum Steady- State Drain

Figure 16. Maximum Safe Operating Area.

Current versus Copper Mounting Pad
Area.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

D = 0.5

0.2

0.1

0.05

0.02

0.01

Single Pulse

t , TIME (sec)

1

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

R (t) = r(t) * R

JA

θ

R = See note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t /t

JA

θ

1

JA

θ

2

NDS8435A Rev.C1

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
CoolFET™
CROSSVOLT™

2

E

CMOS

TM

FACT™
FACT Quiet Series™

®

FAST
FASTr™
GTO™
HiSeC™

ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™

Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8

TinyLogic™
UHC™
VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or
In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.