Page 1
NDS356AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
September 1996
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-1.1 A, -30 V, R
R
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
= 0.3 Ω @ VGS=-4.5 V
DS(ON)
= 0.2 Ω @ VGS=-10 V.
DS(ON)
DS(ON)
.
capability.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS356AP Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) ±1.1 A
- Pulsed ±10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
JC
NDS356AP Rev.C1
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ =55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-0.8 -1.6 -2.5 V
TJ =125°C -0.5 -1.3 -2.2
R
I
g
DS(ON)
D(ON)
FS
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = -4.5 V, ID = -1.1 A
VGS = -10 V, ID = -1.3 A
VGS = -4.5 V, VDS = -5 V
VDS = -5 V, I
= -1.1 A 2 S
D
TJ =125°C
0.25 0.3
0.35 0.4
0.14 0.2
-3 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 170 pF
f = 1.0 MHz
280 pF
Reverse Transfer Capacitance 65 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 17 30 ns
VDD = -10 V, ID = -1 A,
VGS = -10 V, R
GEN
= 50 Ω
Turn - Off Delay Time 53 90 ns
Turn - Off Fall Time 38 80 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.7 nC
Gate-Drain Charge 1.5 nC
VDS = -10 V, ID = -1.1 A,
VGS = -5 V
8 15 ns
3.4 4.4 nC
NDS356AP Rev.C1
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Electrical Characteristics (T
TJ−
T
TJ−
T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Source Current -0.42 A
Maximum Pulsed Drain-Source Diode Forward Current -10 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
A
(t)
=
(t)
R
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
=
R
θJC+RθCA
A
2
(t)
= I
× R
DS(ON)@T
D
(t)
J
VGS = 0 V, IS = -0.42 (Note 2)
-0.8 -1.2 V
is guaranteed by
JC
θ
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1b
NDS356AP Rev.C1
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Typical Electrical Characteristics
D
-10
V = -10V
GS
-8
-6
-4
-2
D
I , DRAIN-SOURCE CURRENT (A)
0
-7.0
-6.0
-5.5
-5.0
-4.5
V , DRAIN-SOURCE VOLTAGE (V)
DS
-4.0
Figure 1. On-Region Characteristics.
1.6
I = -1.1A
D
V = -4.5V
1.4
GS
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
-3.5
-3.0
2
1.8
V = -3.5 V
GS
1.6
1.4
1.2
1
DS(on)
R , NORMALIZED
0.8
0.6
DRAIN-SOURCE ON-RESISTANCE
-5-4-3-2-10
0.4
-4.0
-4.5
-5.0
I , DRAIN CURRENT (A)
D
-5.5
-6.0
-7.0
-10
-10-8-6-4-20
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
2
V = -4.5V
GS
1.8
1.6
1.4
1.2
1
R , NORMALIZEDDS(on)
0.8
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
T = 125°C
J
25°C
-55°C
I , DRAIN CURRENT (A)
-8-6-4-20
Figure 3. On-Resistance Variation
with Temperature.
-5
V = -10V
DS
-4
-3
-2
D
I , DRAIN CURRENT (A)
-1
0
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
T = -55°C
J
25°C
125°C
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
1.2
V = V
DS
GS
I =- 250µA
1.1
1
0.9
GS(th)
V , NORMALIZED
0.8
GATE-SOURCE THRESHOLD VOLTAGE
0.7
-5-4-3-2-1
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
D
Figure 6. Gate Threshold Variation
with Temperature.
NDS356AP Rev.C1
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Typical Electrical Characteristics (continued)
DS
1.08
I = -250µA
D
1.06
1.04
1.02
1
DSS
0.98
BV , NORMALIZED
0.96
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.94
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation with
Temperature.
600
400
300
200
100
CAPACITANCE (pF)
f = 1 MHz
50
V = 0 V
GS
30
0.1 0.2 0.5 1 2 5 10 20
-V , DRAIN TO SOURCE VOLTAGE (V)
C
C
C
iss
oss
rss
5
V = 0V
GS
2
1
0.5
0.1
0.01
0.001
S
-I , REVERSE DRAIN CURRENT (A)
0.0001
0 0.2 0.4 0.6 0.8 1 1.2
-V , BODY DIODE FORWARD VOLTAGE (V)
SD
T = 125°C
J
25°C
-55°C
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
10
I = -1.1A
D
8
6
4
2
GS
-V , GATE-SOURCE VOLTAGE (V)
0
0 1 2 3 4 5 6 7
Q , GATE CHARGE (nC)
g
V = -5V
DS
-10V
-15V
Figure 9. Capacitance Characteristics.
V
DD
V
IN
D
V
GS
R
GEN
G
S
Figure 11. Switching Test Circuit.
Figure 10. Gate Charge Characteristics.
t t
on off
t
R
d(on)
L
V
OUT
V
OUT
r
90%
10%
DUT
t
d(off)
90%
10%
tt
f
90%
V
IN
50%
50%
10%
PULSE WIDTH
INVERTED
Figure 12. Switching Waveforms.
NDS356AP Rev.C1
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Typical Electrical Characteristics (continued)
DS
5
V = - 5VDS
T = -55°C
4
3
J
25°C
125°C
2
1
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
I , DRAIN CURRENT (A)
D
Figure 13. Transconductance Variation with Drain
Current and Temperature.
1
0.8
0.6
1a
1b
0.4
0.2
0
STEADY-STATE POWER DISSIPATION (W)
0 0.1 0.2 0.3 0.4
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
2
20
10
5
2
1
0.5
0.1
D
-I , DRAIN CURRENT (A)
0.05
-5-4-3-2-10
0.01
RDS(ON) LIMIT
V = -4.5V
GS
SINGLE PULSE
R = See Note 1b
JA
θ
T = 25°C
A
A
0.1 0.2 0.5 1 2 5 10 20 30
- V , DRAIN-SOURCE VOLTAGE (V)
Figure 14. Maximum Safe Operating Area.
1.4
1.3
1.2
1a
1.1
1b
1
0.9
D
-I , STEADY-STATE DRAIN CURRENT (A)
0.8
0 0.1 0.2 0.3 0.4
2oz COPPER MOUNTING PAD AREA (in )
10ms
100ms
1s
DC
4.5"x5" FR-4 Board
T = 25 C
A
Still Air
V = -4.5V
GS
100us
1ms
o
2
Figue 15. SuperSOT
TM _
3 Maximum
Steady-State Power Dissipation versus
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
Copper Mounting Pad Area.
1
D = 0.5
0.5
R (t) = r(t) * R
JA
0.2
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
Single Pulse
t , TIME (sec)
1
θ
R = See Note 1b
θJA
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t /t
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
JA
θ
θ
JA
1
2
NDS356AP Rev.C1
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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EnSigna
TM
TM
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STAR*POWER is used under license
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FASTr™
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OPTOPLANAR™
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Power247™
PowerTrench
QFET™
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QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
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STAR*POWER™
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DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Formative or
In Design
First Production
Full Production
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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